Clock, Reset, and Power Control (CRP)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
5-18
Freescale Semiconductor
Preliminary
instruction on the active core will initiate entry into the low-power mode. At this point, the CRP takes over
operation of the SoC until a wakeup event occurs.
5.3.2.1
CRP Clock Selection
In both sleep or stop modes, the CRP control logic is clocked by the 16 MHz IRC. The RTC/API can be
clocked by either the 32 kHz IRC, the 32 kHz XOSC, or the 16 MHz IRC. The pin wakeup logic can be
clocked by either the 32 kHz IRC, or the 16 MHz IRC. These clock source selections must be made prior
to executing both WAIT instructions to the cores.
5.3.2.2
Sleep Mode RAM Retention
The RAMSEL bits in the CRP_PSCR register determine the amount of RAM that remains powered in
sleep mode. This selection must be made prior to executing the WAIT instructions to the cores with the
CRP_PSCR[SLEEP] bit set.
5.3.3
Low-Power Operation
After the WAIT instructions have been executed with either the sleep or stop bit set, and the cores have
cleanly halted, the clock control block signals the CRP to enter the selected low-power mode. Note that if
both the sleep and stop bits are set, sleep will be the mode entered.
At this point, the CRP has complete control of the SoC.
gives the sequence to transition from
RUN mode to SLEEP/STOP.
give the transition diagram for going from RUN
mode to sleep, and then back to RUN mode.
mode to stop, and back to RUN mode. The CRP does not support going directly to/from Sleep mode
from/to stop mode.
