Inter-Integrated Circuit Bus Controller Module (I
2
C)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
27-4
Freescale Semiconductor
Preliminary
•
Repeated start signal generation
•
Acknowledge bit generation/detection
•
Bus busy detection
•
Basic DMA interface
Features currently not supported:
•
No support for general call address
•
Not compliant to ten-bit addressing
27.1.4
Modes of Operation
There are two operating modes of the I
2
C module: run mode and stop mode. In run mode, I
2
C_A = 0 in
the SIU_HLT register and all functional parts of the I
2
C module are running. In stop mode, I
2
C_A = 1 in
the SIU_HLT register and all clocks to the I
2
C module are disabled.
27.2
External Signal Description
Refer to
Section 2.7, “Detailed External Signal Descriptions
,” for detailed signal
descriptions.
27.3
Memory Map and Registers
This section provides a detailed description of all I
2
C registers.
27.3.1
Module Memory Map
shows the I
2
C memory map. The address of each register is given as an offset to the I
2
C base
address. Registers are listed in address order, identified by complete name and mnemonic, and lists the
type of accesses allowed. There are no MPC5510-specific register definitions for the I
2
C module.
Table 27-1. I
2
C Memory Map
Offset from
I
2
C_BASE
(0xFFF8_8000)
Register
Access
Reset Value
Section/Page
0x0000
IBAD — I
2
C bus address register
R/W
0x0000
0x0001
IBFD — I
2
C bus frequency divider register
R/W
0x0000
0x0002
IBCR — I
2
C bus control register
R/W
0x0080
0x0003
IBSR — I
2
C bus status register
R/W
0x0080
0x0004
IBDR — I
2
C bus data I/O register
R/W
0x0000
0x0005
IBIC — I
2
C bus interrupt config register
R/W
0x0000
0x0006–0x3FFF
Reserved
R
0x0000
N/A
