Deserial Serial Peripheral Interface (DSPI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
23-35
Preliminary
The POPNXTPTR field in the DSPI
x
_SR points to the RX FIFO entry that is returned when the
DSPI
x
_POPR is read. The POPNXTPTR contains the positive, 32-bit word offset from DSPI
x
_RXFR0.
For example, POPNXTPTR equal to two means that the DSPI
x
_RXFR2 contains the received SPI data
that will be returned when DSPI
x
_POPR is read. The POPNXTPTR field is incremented every time the
DSPI
x
_POPR is read. POPNXTPTR rolls over every four frames on the MCU.
23.4.3.5.1
Filling the RX FIFO
The RX FIFO is filled with the received SPI data from the shift register. While the RX FIFO is not full,
SPI frames from the shift register are transferred to the RX FIFO. Every time an SPI frame is transferred
to the RX FIFO the RX FIFO counter is incremented by one.
If the RX FIFO and shift register are full and a transfer is initiated, the RFOF bit in the DSPI
x
_SR is
asserted indicating an overflow condition. Depending on the state of the ROOE bit in the DSPI
x
_MCR,
the data from the transfer that generated the overflow is ignored or shifted in to the shift register. If the
ROOE bit is asserted, the incoming data is shifted in to the shift register. If the ROOE bit is negated, the
incoming data is ignored.
23.4.3.5.2
Draining the RX FIFO
Host software or the eDMA can remove (pop) entries from the RX FIFO by reading the DSPI
x
_POPR. For
more information on DSPI
x
_POPR, refer to
Section 23.3.2.7, “DSPI POP RX FIFO Register
x
_POPR decrements the RX FIFO counter by one. Attempts to pop
data from an empty RX FIFO are ignored, the RX FIFO counter remains unchanged. The data returned
from reading an empty RX FIFO is undetermined.
When the RX FIFO is not empty, the RX FIFO drain flag (RFDF) in the DSPI
x
_SR is set. The RFDF bit
is cleared when the RX_FIFO is empty and the eDMA controller indicates that a read from DSPI
x
_POPR
is complete; alternatively the RFDF bit can be cleared by the host writing a 1 to it.
23.4.4
Deserial Serial Interface (DSI) Configuration
The DSI configuration supports pin-count reduction by serializing eMIOS output channels or register bits
and shifting them out in an SPI-like protocol. The timing and transfer protocol is described in
Section 23.4.8, “Transfer Formats
.” The received serial frames are converted to a parallel form
(deserialized) and placed on the eMIOS input channels or in a register. See
,” for the source of the serialization data for each DSPI block.
The various features of the DSI configuration are set in the DSPI
x
_DSICR. For more information on the
DSPI
x
_DSICR, refer to
Section 23.3.2.10, “DSPI DSI Configuration Register (DSPI_DSICR)
.” The DSPI
is in DSI configuration when the DCONF field in the DSPI
x
_MCR is 0b01.
The DSI frames can be from four to 16 bits long.
shows an example of how a master DSPI connects to a SPI slave in DSI configuration.
