Enhanced Serial Communication Interface (eSCI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
24-27
Preliminary
24.4.4.5.1
Slow Data Tolerance
shows how much a slow received frame can be misaligned without causing a noise error or
a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data
samples at RT8, RT9, and RT10.
Figure 24-19. Slow Data
For an 8-bit data character, data sampling of the stop bit takes the receiver RT clock 151 clock cycles, as
is shown below:
With the misaligned character shown in
, the receiver counts 151 RT cycles at the point when
the count of the transmitting device is 9 bits multiplied by 16 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data
character with no errors is 4.63%, as is shown below:
For a 9-bit data character, data sampling of the stop bit takes the receiver 167 RT cycles, as is shown below:
With the misaligned character shown in
, the receiver counts 167 RT cycles at the point when
the count of the transmitting device is 10 bit multiplied by 16 RT cycles = 160 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit
character with no errors is 4.19%, as is shown below:
24.4.4.5.2
Fast Data Tolerance
shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10
instead of RT16 but remains sampled at RT8, RT9, and RT10.
RT1
Receiver
RT clock
RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16
MSB
STOP
Data samples
9 bit times
16 RT cycles
7 RT cycles
+
×
151 RT cycles
=
151 – 144
151
--------------------------
100
×
4.63%
=
10 bit times
16 RT cycles
7 RT cycles
+
×
167 RT cycles
=
167 – 160
167
--------------------------
100
×
4.19%
=
