Enhanced Serial Communication Interface (eSCI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
24-20
Freescale Semiconductor
Preliminary
24.4.3.2
Character Transmission
To transmit data, the MCU writes the data bits to the eSCI data register (ESCI
x
_DR), which in turn are
transferred to the transmit shift register. The transmit shift register then shifts a frame out through the TXD
signal, after it has prefaced them with a start bit and appended them with a stop bit. The eSCI data register
(ESCI
x
_DR) is the buffer (write-only during transmit) between the internal data bus and the transmit shift
register.
The eSCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from
the buffer (ESCI
x
_DR) to the transmit shift register. The transmit driver routine may respond to this flag
by writing another byte to the transmitter buffer (ESCI
x
_DR), while the shift register remains shifting out
the first byte.
To initiate an eSCI transmission:
1. Clear ESCI
x
_CR2[MDIS] bit, if this bit is set, to enable the eSCI_
x
module.
2. Configure the eSCI with single 32-bit write to ESCI
x
_CR1:
c) Write to ESCIx_CR1[SBR] to start the baud generator with a target baud rate.
d) Write to ESCIx_CR1 to configure word length, parity, and other configuration bits (LOOPS,
RSRC, M, WAKE, ILT, PE, PT).
e) Write to ESCIx_CR1 to enable the transmitter, receiver, interrupts, and wakeup as required
(TIE, TCIE, RIE, ILIE, TE, RE, RWU, SBK). A preamble or idle character will now be shifted
out of the transmitter shift register.
3. Transmit procedure for each byte:
a) Poll the TDRE flag by reading the ESCI
x
_SR or responding to the TDRE interrupt. Remember
that the TDRE bit resets to 1.
b) If the TDRE flag is set, write the data to be transmitted to ESCI
x
_DR, where the ninth bit is
written to the T8 bit in ESCI
x
_DR if the eSCI is in 9-bit data format. A new transmission will
not result until the TDRE flag has been cleared.
4. Repeat step 3 for each subsequent transmission.
NOTE
The TDRE flag is set when the shift register is loaded with the next data to
be transmitted from ESCI
x
_DR, which occurs approximately halfway
through the stop bit of the previous frame. Specifically, this transfer occurs
9/16ths of a bit time AFTER the start of the stop bit of the previous frame.
Toggling the TE bit from 0 to 1 automatically loads the transmit shift register with a preamble of 10 logic
1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from
the eSCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least
significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit
position.
The eSCI hardware supports odd or even parity. When parity is enabled, the most significant bit (msb) of
the data character is the parity bit.
