Miscellaneous Control Module (MCM)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
16-7
Preliminary
If the software watchdog timer is enabled (SWTCR[SWE] = 1), then any write of a data value other than
0x55 or 0xAA generates an immediate system reset, regardless of the value in the SWTCR[SWRI] field.
16.2.2.3
SWT Interrupt (SWTIR)
All interrupt requests associated with MCM are collected in the SWTIR register. This includes the
software watchdog timer interrupt.
During the appropriate interrupt service routine handling these requests, the interrupt source contained in
the SWTIR must be explicitly cleared (see
For certain values of the SWTCR[SWRI] field, the software watchdog timer generates an interrupt
response to a time-out. For these configurations, the SWTIR provides the program-visible interrupt request
from the software watchdog timer.
16.2.2.4
Miscellaneous User-Defined Control Register (MUDCR)
The MUDCR provides a program-visible register. On MPC5510, one bit is implemented. The PRI bit
determines whether the AXBS-lite uses a fixed or round robin priority arbitration scheme for masters
requesting access to AXBS-lite slave ports. See
for the miscellaneous
user-defined control register definition.
Offset: MCM_BAS 0x001F
Access: User read/write
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
SWTIC
W
w1c
Reset
0
0
0
0
0
0
0
0
Figure 16-3. SWT Interrupt (SWTIR)
Table 16-4. SWTIR Field Descriptions
Field
Description
bits 0–6
Reserved.
SWTIC
Software Watchdog Interrupt Flag.
0 A SWT interrupt has not occurred.
1 A SWT interrupt has occurred. The interrupt request is negated by writing a 1 to this bit. Writing a 0 has no
effect.
