Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
31-63
Preliminary
31.4.5.5
ADC Control Logic Overview and Command Execution
shows the basic logic blocks involved in the ADC control and how they interact.
CFIFOs/RFIFOs interact with ADC command/result message return logic through the FIFO control unit.
The EB and BN bits in the command message uniquely identify the ADC to which a command should be
sent. The FIFO control unit decodes these bits and sends the ADC command to the proper ADC. Other
blocks of logic are the result format and calibration submodule, the time stamp logic
,
and the MUX control
logic.
The result format and calibration submodule formats the returning data into result messages and sends
them to the RFIFOs. The returning data can be data read from an ADC register, a conversion result, or a
time stamp. The formatting and calibration of conversion results also take place inside this submodule.
The time stamp logic latches the value of the time base counter when detecting the end of the analog input
voltage sampling, and sends it to the result format and calibration submodule as time stamp information.
The MUX control logic generates the proper MUX control signals and, when the ADC0/1_EMUX bits are
asserted, the MA signals based on the channel numbers extracted from the ADC Command.
ADC commands are stored in the ADC command buffers (2 entries) as they come in and they are executed
on a first-in-first-out basis. After the execution of a command in ENTRY1 finishes, all commands are
shifted one entry. After the shift, ENTRY0 is always empty and ready to receive a new command.
Execution of configuration commands only starts when they reach ENTRY1. Consecutive conversion
commands are pipelined, and their execution can start while in ENTRY0. This is explained below.
A/D conversion accuracy can be affected by the settling time of the input channel multiplexers. Some time
is required for the channel multiplexer’s internal capacitances to settle after the channel number is
changed. If the time prior to and during sampling is not long enough to permit this settling, then the voltage
on the sample capacitors will not accurately represent the voltage to be read. This is a problem in particular
when external muxes are used.
Table 31-35. Correspondence between Binary and Decimal Representations of the Gain Constant
Gain Constant
(GCC_INT.GCC_FRAC binary format)
Corresponding Decimal Value
0.0000_0000_0000_00
0
...
...
0.1000_0000_0000_00
0.5
...
...
0.1111_1111_1111_11
0.999938...
1.0000_0000_0000_00
1
...
...
1.1100_0000_0000_00
1.75
...
...
1.1111_1111_1111_11
1.999938...
