FlexRay Communication Controller (FLEXRAY)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
30-59
Preliminary
30.5.2.53 Receive FIFO Depth and Size Register (RFDSR)
This register defines the structure of the selected FIFO, i.e. the number of entries and the size of each entry.
30.5.2.54 Receive FIFO A Read Index Register (RFARIR)
This register provides the message buffer header index of the next available receive FIFO A entry that the
application can read.
Table 30-63. RFSIR Field Descriptions
Field
Description
SIDX
Start Index. This field defines the number of the message buffer header field of the first message buffer of the
selected receive FIFO. The FlexRay block uses the value of the SIDX field to determine the physical location of
the receiver FIFO’s first message buffer header field.
Base + 0x008A
Write:
POC:config
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
FIFO_DEPTH
0
ENTRY_SIZE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 30-53. Receive FIFO Depth and Size Register (RFDSR)
Table 30-64. RFDSR Field Descriptions
Field
Description
FIFO_DEPTH FIFO Depth. This field defines the depth of the selected receive FIFO, i.e. the number of entries.
ENTRY_SIZE Entry Size. This field defines the size of the frame data sections for the selected receive FIFO in 2 byte entities.
Base + 0x008C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
RDIDX
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 30-54. Receive FIFO A Read Index Register (RFARIR)
Table 30-65. RFARIR Field Descriptions
Field
Description
RDIDX
Read Index. This field provides the message buffer header index of the next available receive FIFO message
buffer that the application can read. The FlexRay block increments this index when the application writes to the
FNEAIF flag in the
Global Interrupt Flag and Enable Register (GIFER)
. The index wraps back to the first
message buffer header index if the end of the FIFO was reached.
