Nexus Development Interface (NDI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
20-6
Freescale Semiconductor
Preliminary
20.3
External Signal Description
With the exception of the JCOMP signal, all signals are shared by all the individual blocks that make up
the NDI block. The Nexus port controller (NPC) block controls the signal sharing. The JCOMP signal is
input to the NPC block and used to generate the Nexus reset control signal.
Refer to
Section 2.7, “Detailed External Signal Descriptions
,” for detailed signal
descriptions.
20.3.1
Nexus Signal Reset States
20.4
Memory Map and Registers
The NDI block contains no memory-mapped registers. Nexus registers are accessed by a development tool
via the JTAG port using a client-select value and a register index. OnCE registers are accessed by loading
the appropriate value in the RS field of the OnCE command register (OCMD) via the JTAG port.
20.4.1
Nexus Debug Interface Registers
shows the NDI registers by client select and index values. OnCE register addressing is
documented in
Chapter 19, “IEEE 1149.1 Test Access Port Controller (JTAGC)
Table 20-1. NDI Signal Reset State
Name
Function
Nexus Reset
State
Pull
EVTI
Event-in pin
—
Up
EVTO
Event-out pin
0b1
—
MCKO
Message clock out pin
0b0
—
MDO[3:0]
or
MDO[7:0]
Message data out pins
0
1
1
MDO[0] reflects the state of the internal power on reset signal until RESET is
negated.
—
MSEO
Message start/end out pins
0b11
—
Table 20-2. Nexus Debug Interface Registers
Client Select
Index
Register
Client-Independent Registers
0bxxxx
0
Device ID (DID)
1
0bxxxx
1
Client select control (CSC)
0bxxxx
127
Port configuration register (PCR)
e200z0 Control/Status Registers
0b0000
2
e200z0 development control1 (DC1)
