IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
19-12
Freescale Semiconductor
Preliminary
19.5.2.1
Enabling the TAP Controller
To access the e200z0 OnCE controller, the proper JTAGC instruction needs to be loaded in the JTAGC
instruction register, as discussed in
Section 19.1.3.4, “TAP Sharing Mode
”. The e200z0 OnCE TAP
controller may either be accessed independently or chained with the e200z1 OnCE TAP controller, such
that the TDO output of the e200z1 TAP controller is fed into the TDI input of the e200z0 TAP controller.
The chained configuration allows commands to be loaded into both core’s OnCE registers in one shift
operation, so that both cores can be sent a GO command at the same time for example.
19.5.3
e200z0 OnCE Controller Register Descriptions
Most e200z0 OnCE debug registers are fully documented in the
e200z0 Reference Manual
. The MPC5510
implements a new shared nexus control register (SNC) which is defined in
Shared Nexus Control Register (SNC)
The SNC register is used to configure which core is being traced by the block, and how the
outputs of the block affect each core.
The SNC register requires a new encoding in the OnCE command register’s register select field
(OCMD[RS]), as defined in
Section 19.5.3.1, “OnCE Command Register (OCMD)
19.5.3.1
OnCE Command Register (OCMD)
The OnCE command register (OCMD) is a 10-bit shift register that receives its serial data from the TDI
pin and serves as the instruction register (IR). It holds the 10-bit commands to be used as input for the
e200z0 OnCE Decoder. The OCMD is shown in
. The OCMD is updated when the TAP
controller enters the update-IR state. It contains fields for controlling access to a resource, as well as
controlling single-step operation and exit from OnCE mode.
Although the OCMD is updated during the update-IR TAP controller state, the corresponding resource is
accessed in the DR scan sequence of the TAP controller, and as such, the update-DR state must be
transitioned through in order for an access to occur. In addition, the update-DR state must also be
transitioned through in order for the single-step and/or exit functionality to be performed, even though the
command appears to have no data resource requirement associated with it.
0
1
2
3
4
5
6
7
8
9
R
R/W
GO
EX
RS
W
Reset:
0
0
0
0
0
1
1
0
1
1
Figure 19-8. OnCE Command Register (OCMD)
Table 19-3. e200z0 OnCE Register Addressing
RS
Register Selected
000 0000 – 000 0001
Reserved
000 0010
JTAG ID (read-only)
