Flash Array and Control
MPC5510 Microcontroller Family Reference Manual, Rev. 1
22-10
Freescale Semiconductor
Preliminary
NOTE
If blocks are not present (due to configuration or total memory size), the
LOCK bits will default to locked, and will not be writable. The reset value
will always be 1 (independent of the shadow block) and register writes will
have no effect.
Offset: FLASH_REG 0x0004
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R LME
0
0
0
0
0
0
0
0
0
0
SLOCK
1
1
MLOCK[1:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
1
1
1
1
1
1
LLOCK[9:0]
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 22-5. Low-/Mid-Address Space Block Locking Register (LML)
Table 22-5. LML Field Descriptions
Field
Description
LME
Low- and Mid-Address Lock Enable. Enables the locking register fields (SLOCK, MLOCK, and LLOCK) to be set
or cleared by register writes. This bit is a status bit only. It may not be written or cleared and the reset value is 0.
To set this bit, write a password and if the password matches, the LME bit will be set to reflect the status of
enabled. It is enabled until a reset operation occurs. For LME, the password 0xA1A1_1111 must be written to the
LML.
0 Low- and mid-address locks are disabled, and cannot be modified
1 Low- and mid-address locks are enabled and can be written
bits 1–10
Reserved.
SLOCK
Shadow Lock. Locks the shadow row from programs and erases. The SLOCK bit is not writeable if a high-voltage
operation is suspended.
Upon reset, information from the shadow row is loaded into the SLOCK bit. The SLOCK bit may be written as a
register. Reset will cause the bits to go back to their shadow row value. The default value of the SLOCK bit
(assuming the corresponding shadow row bit is erased) would be locked. SLOCK is not writable unless LME is
high.
0 Shadow row is available to receive program and erase pulses.
1 Shadow row is locked for program and erase.
bits 12–13
Reserved.
