Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
31-45
Preliminary
A triggered CFIFO with commands bound for a certain command buffer consecutively transfers its
commands to the buffer until one of the following occurs:
•
An asserted end of queue bit is reached.
•
An asserted pause bit is encountered and the CFIFO is configured for edge trigger mode.
•
CFIFO is configured for level trigger mode and a closed gate is detected.
•
In case its commands are bound for an internal command buffer, a higher priority CFIFO that uses
the same internal buffer is triggered.
The prioritization logic of the eQADC, depicted in
, that prioritizes CFIFOs with commands
bound for ADC0.
NOTE
Triggered but empty CFIFOs, underflowing CFIFOs, are not considered for
prioritization. No data from these CFIFOs will be sent to the on-chip ADC,
nor will they stop lower priority CFIFOs from transferring commands.
Whenever CBuffer0 is able to receive new commands, the prioritization submodule selects the
highest-priority triggered CFIFO with a command bound for ADC0, and sends it to ADC0. If CBuffer0 is
able to receive new entries but there are no triggered CFIFOs with commands bound for it, nothing is sent.
Figure 31-29. CFIFO Prioritization Logic
31.4.3.3
External Trigger from eTPU or eMIOS Channels
The six eQADC external trigger inputs can be connected to either an external pin (either ETRIG0,
ETRIG1, GPIO206, or GPIO207), an eTPU channel, or an eMIOS channel. The input source for each
eQADC external trigger is individually specified in the eQADC trigger input select register (SIU_ETISR)
in the SIU block.
eQADC
Prioritization
Logic
6 x Command
Command
CFIFO0
Command
CFIFO1
Command
CFIFO2
Command
CFIFO3
Command
CFIFO4
Command
CFIFO5
ADC0
Command Buffer0
(2 Entries)
Prioritization
for ADC0
Usage
Command
