e200z0 Core (Z0)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
11-4
Freescale Semiconductor
Preliminary
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32-bit AU for arithmetic and comparison operations
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32-bit LU for logical operations
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32-bit priority encoder for count leading zero’s function
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32-bit single cycle barrel shifter for shifts and rotates
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32-bit mask unit for data masking and insertion
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Divider logic for signed and unsigned divide in 5 to 34 clocks with minimized execution timing
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8x32 hardware multiplier array supports 1 to 4 cycle 32x32->32 multiply (early out)
11.2.3
Load/Store Unit Features
The e200 load/store unit supports load, store, and the load multiple / store multiple instructions:
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32-bit effective address adder for data memory address calculations
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Pipelined operation supports throughput of one load or store operation per cycle
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32-bit interface to memory
11.2.4
e200z0 System Bus Features
The features of the e200z0 System Bus interface are as follows:
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Unified instruction/data bus
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32-bit address bus plus attributes and control
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Separate uni-directional 32-bit read data bus and 32-bit write data bus
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Overlapped, in-order accesses
11.3
Core Registers and Programmer’s Model
This section describes the registers implemented in the e200z0 core. It includes an overview of registers
defined by the Power Architecture Book E architecture, highlighting differences in how these registers are
implemented in the e200 core, and provides a detailed description of e200-specific registers. Full
descriptions of the architecture-defined register set are provided in Power Architecture Book E
Specification.
The Power Architecture Book E defines register-to-register operations for all computational instructions.
Source data for these instructions are accessed from the on-chip registers or are provided as immediate
values embedded in the opcode. The three-register instruction format allows specification of a target
register distinct from the two source registers, thus preserving the original data for use by other
instructions. Data is transferred between memory and registers with explicit load and store instructions
only.
show the e200 register set including the registers which are accessible while
in supervisor mode, and the registers which are accessible in user mode. The number to the right of the
special-purpose registers (SPRs) is the decimal number used in the instruction syntax to access the register
(for example, the integer exception register (XER) is SPR 1).
