External Bus Interface (EBI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
29-35
Preliminary
Figure 29-23. Burst 32-Bit Read Cycle, Zero Wait States
Figure 29-24. Burst 32-Bit Read Cycle, One Initial Wait State
29.4.2.5.1
TBDIP Effect on Burst Transfer
Some memories require different timing on the BDIP signal than the default to run burst cycles. Using the
default value of TBDIP = 0 in the appropriate EBI base register results in BDIP being asserted (SCY+1)
cycles after the address transfer phase, and being held asserted throughout the cycle regardless of the wait
states between beats (BSCY).
shows an example of the TBDIP = 0 timing for a 4-beat burst
with BSCY = 1.
CLKOUT
ADDR[8:31]
BDIP
DATA[0:31]
TA
RD_WR
TS
OE
CSn
Expects more data
ADDR[29:31] = ‘000’
DATA is valid
Wait state
CLKOUT
ADDR[8:31]
BDIP
DATA[0:31]
TA
RD_WR
TS
OE
CSn
Expects more data
ADDR[29:31] = ‘000’
DATA is valid
