Frequency Modulated Phase Locked Loop (FMPLL)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
4-4
Freescale Semiconductor
Preliminary
LOLF
Loss- of-Lock Flag. This bit provides the interrupt request flag. To clear the flag, write a 1 to the bit. Writing 0 has
no effect. This flag will not be set, and an interrupt will not be requested, if the loss-of-lock condition was caused
by a system reset, enabling frequency modulation, or write to the ESYNCR1 which modifies the
ESYNCR1[EMFD] bits. If the flag is set due to a system failure, writing the ESYNCR1[EMFD] bits or enabling FM
will not clear the flag. Assert reset to clear the flag. If lock is reacquired, the bit will remain set until either a write
1 or reset is asserted.
1 Interrupt service requested
0 Interrupt service not requested
LOC
Loss-Of-Clock Status. The LOC bit is an indication of whether a loss-of-clock condition is present when operating
in normal PLL mode. If LOC=0, the system clocks are operating normally. If LOC=1, the system clocks have failed
due to a reference failure or a PLL failure. If the read of the LOC bit and the loss-of-clock condition occur
simultaneously, the bit does not reflect the current loss-of-clock condition. If a loss-of-clock condition occurs that
sets this bit and the clocks later return to normal, this bit will be cleared. LOC is always zero in PLL Off mode.
1 Clocks are not operating normally
0 Clocks are operating normally
MODE
Clock Mode. The initial value for the MODE bit is determined at reset. The state of this bit, along with PLLSEL
and PLLREF, indicates which clock mode the PLL is operating in (see
). The value of
ESYNCR1[CLKCFG0] will be reflected in this location.
1 PLL clock mode
0 PLL Off mode
PLLSEL
PLL Mode Select. The initial value for the PLLSEL bit is determined at reset. The state of this bit, along with
MODE and PLLREF, indicates which mode the PLL operates in (see
). This bit is cleared in PLL Off
mode. The value of ESYNCR1[CLKCFG1] will be reflected in this location.
1 Normal PLL mode
0 PLL Off mode
PLLREF
PLL Clock Reference Source. The initial value for the PLLREF bit is determined at reset. The state of this bit,
along with MODE and PLLSEL, indicates which reference source has been chosen for normal PLL mode (see
). This bit is cleared in PLL Off mode. The value of ESYNCR1[CLKCFG2] will be reflected in this
location.
1 Crystal clock reference chosen
0 External clock reference chosen
Note: User must also use the XOSC bit in the CRP register (CRP_CLKSRC) to enable the 4 to 40 MHz oscillator.
LOCKS
Sticky PLL Lock Status Bit. The LOCKS bit is a sticky indication of PLL lock status. LOCKS is set by the lock
detect circuitry when the PLL acquires lock after: 1) a system reset, or 2) a write to the ESYNCR2 which modifies
the ESYNCR2[EMFD] bits, or 3) frequency modulation is enabled. Whenever the PLL loses lock, LOCKS is
cleared. LOCKS remains cleared after the PLL re-locks, until one of the three conditions occurs. Furthermore, if
the LOCKS bit is read when the PLL simultaneously loses lock, the bit does not reflect the current loss-of-lock
condition.
If operating in PLL Off mode, LOCKS remains cleared after reset.
1 PLL has not lost lock since last system reset, a write to ESYNCR1 to modify the ESYNCR1[EMFD] bit field,
or frequency modulation enabled
0 PLL has lost lock since last system reset, a write to ESYNCR1 to modify the ESYNCR1[EMFD] bit field, or
frequency modulation enabled
Table 4-2. SYNSR Register Field Descriptions (continued)
Field
Description
