Deserial Serial Peripheral Interface (DSPI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
23-23
Preliminary
23.3.2.7
DSPI POP RX FIFO Register (DSPI_POPR)
The DSPI_POPR provides a means to read the RX FIFO. See
Section 23.4.3.5, “Receive First-In First-Out
,” for a description of the RX FIFO operations. Eight- or 16-bit read
accesses to the DSPI_POPR will read from the RX FIFO and update the counter and pointer.
NOTE
The DSPI_POPR must not be read speculatively. For future compatibility,
the TLB (MMU table) entry covering the DSPI_POPR must be configured
to be guarded.
23.3.2.8
DSPI Transmit FIFO Registers 0–3 (DSPI_TXFRn)
The DSPI_TXFR
n
registers provide visibility into the TX FIFO for debugging purposes. Each register is
an entry in the TX FIFO. The registers are read-only and cannot be modified. Reading the DSPI_TXFR
n
registers does not alter the state of the TX FIFO. The MCU uses four registers to implement the TX FIFO,
that is DSPI_TXFR0–DSPI_TXFR3 are used.
Offset: DSP 0x0038
Access: Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
RXDATA
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23-8. DSPI POP RX FIFO Register (DSPI_POPR)
Table 23-8. DSPI_POPR Field Descriptions
Field
Description
bits 0–15 Reserved.
RXDATA Received Data. The RXDATA field contains the SPI data from the RX FIFO entry pointed to by the pop next data
pointer (POPNXTPTR).
