Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
31-72
Freescale Semiconductor
Preliminary
31.4.8.2
Analog-to-Digital Converter (ADC)
31.4.8.2.1
ADC Overview
Figure 31-43. RSD ADC Block Diagram
The redundant signed digit (RSD) cyclic ADC consists of two main portions, the analog RSD stage, and
the digital control and calculation module, as shown in
. To begin an analog-to-digital
conversion, an input voltage is passed into the analog RSD stage and then from the RSD stage output, back
to its input to be passed again. To complete a 12-bit conversion, the signal must pass through the RSD stage
13 times. Each time an input signal is read into the RSD stage, a digital sample is taken by the digital
control/calculation module. The digital control/calculation module uses this sample to tell the analog
module how to condition the signal. The digital module also saves each successive sample and adds them
according to the RSD algorithm at the end of the entire conversion cycle.
On each pass through the RSD stage, the input signal will be multiplied by exactly two, and summed with
either –vref, 0, or vref, depending on the logic control. The logic control will determine –vref, 0, or vref
depending on the two comparator inputs. As the logic control sets the summing operation, it also sends a
digital value to the RSD adder. Each time an analog signal passes through the RSD single-stage, a digital
value is collected by the RSD adder. At the end of an entire AD conversion cycle, the RSD adder uses these
collected values to calculate the 12-bit digital output.
shows the transfer function for the RSD stage. Note how the digital value (AB) is dependent
on the two comparator inputs.
+
–
Vrefl
Logic
Control
+
–
Vrefh
Digital
Signal
RSD
Adder
–vref,0,vref
Sum
x2
Residue Voltage
Input Voltage
RSD Stage
