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System Clock Description

MPC5510 Microcontroller Family Reference Manual, Rev. 1

Freescale Semiconductor

3-7

Preliminary

3.5.2

Halt Clock Gating

System clock gating is forced via the centralized halt mechanism. The SIU_HLT register’s bits
corresponding to individual modules are configured to determine which modules are clock gated.

The HLT bits are used to drive the stop inputs to the modules. After the module completes a clean
shutdown, the module asserts the stop acknowledge handshake. The stop acknowledge is visible in the
SIU_HLTACK read-only register bits. The modules are individually controlled and halted.

The halted module recovers when the HLT bit is cleared by software. After HLT is cleared, the device’s
logic will re-enable the clocks to the modules and negate the stop signal after the required timing has been
met.

There is no hardware disable for the eDMA and FlexRay modules. Thus before setting the HLT bits for
these masters, software should take actions to prepare for the eDMA and FlexRay clocks to be stopped.
Then software sets the HLT bits for the eDMA and FlexRay to indicate to the clock logic that the clocks
to these modules can now be stopped.

When the HLT bits for the eDMA and FlexRay are set and when the Z0 and Z1 have executed WAIT
instructions, then the clocks to the platform are also gated. The platform logic includes the MPU, AXBS,
AIPS, and MCM. The INTC and SIU are not clock gated to allow for an interrupt to be used to exit WAIT.

3.5.3

Core WAIT Clock Gating

Core clock gating is enabled via the CPU WAIT instruction (or, if the core is in reset, by the CRP Core
Reset bit).

The Z1 and Z0 cores may be idled by their WAIT instructions. The WAIT instructions are used as a
power-saving feature to halt the core. Executing the WAIT instruction puts the corresponding core in an
idle state at a clean transition point. When the core stops, clocks to the core are gated off, and the core

Table 3-2. Software-Controlled Clock Gating Support

Block Name

Register Name

Bit Name

DSPI

MCR

MDIS

ESCI

MCR

MDIS

FlexCAN

MCR

MDIS

EMIOS

MCR

MDIS

EBI

MCR

MDIS

MLB

MCR

MDIS

PIT_RTI

MCR

MDIS

1

1

Only the PIT timers are disabled by MDIS. The RTI is not affected by MDIS.

I

2

C

IBCR

MDIS

NPC

MCR

MCKO_EN, MCKO_GT

Flash Array

MCR

STOP

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Summary of Contents for MPC5510

Page 1: ...rights reserved Freescale Semiconductor MPC5510RM Rev 1 1 04 2012 This is the MPC5510 Reference Manual set consisting of the following files MPC5510 Reference Manual Addendum Rev 1 MPC5510 Reference...

Page 2: ...the MPC5510 Microcontroller Reference Manual order number MPC5510RM For convenience the addenda items are grouped by revision Please check our website at http www freescale com powerarchitecture for t...

Page 3: ...MPC5510 supports system level clock dividers static clock gating using peripheral level module disable MDIS bits and a system level halt mechanism Figure 3 2 shows the device level clock gating mechan...

Page 4: ...lock Module clock MCKO MCKO divider CLK_SRC MDIS FlexRAY Protocol clock CLK_SRC MDIS FlexCAN_A LPCLKDIV0 MDIS DSPI_A MDIS ESCI_A IIC_A PIT RTI Protocol clock CLK_SRC MDIS FlexCAN_B F LPCLKDIV2 CLKOUT...

Page 5: ...eset request has negated and the device is still in the resulting reset and then an external reset is requested both the original reset type and external reset status bits will be set In this case the...

Page 6: ...al trigger is individually specified in the IMUX Select Register 0 SIU_ISEL0 Figure 6 50 gives an example of the multiplexing of an eQADC external trigger input As shown in the figure the ETRIG 0 inpu...

Page 7: ...rpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitatio...

Page 8: ...MPC5510 Microcontroller Family Reference Manual Devices Supported MPC5517G E S MPC5516G E S MPC5515S MPC5514G E Document Number MPC5510RM Rev 1 06 2008 PRELIMINARY...

Page 9: ...arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters tha...

Page 10: ...l Descriptions 2 16 2 7 1 Port A Pins 2 16 2 7 2 Port B Pins 2 17 2 7 3 Port C Pins 2 19 2 7 4 Port D Pins 2 21 2 7 5 Port E Pins 2 24 2 7 6 Port F Pins 2 25 2 7 7 Port G Pins 2 28 2 7 8 Port H Pins 2...

Page 11: ...L 4 1 Introduction 4 1 4 1 1 Block Diagram 4 1 4 1 2 Features 4 2 4 1 3 Modes of Operation 4 2 4 2 External Signal Description 4 2 4 3 Memory Map and Registers 4 2 4 3 1 Module Memory Map 4 3 4 3 2 Re...

Page 12: ...SIU 6 1 Introduction 6 1 6 1 1 Block Diagram 6 1 6 1 2 Features 6 2 6 1 3 Modes of Operation 6 3 6 2 External Signal Description 6 4 6 2 1 Detailed Signal Descriptions 6 4 6 3 Memory Map and Registers...

Page 13: ...atures 9 1 9 1 2 Block Diagram 9 2 9 1 3 Modes of Operation 9 4 9 2 Signal Description 9 5 9 3 Memory Map and Registers 9 5 9 3 1 Module Memory Map 9 5 9 3 2 Register Descriptions 9 6 9 4 Functional D...

Page 14: ...ation 10 13 10 4 2 Translation Lookaside Buffer 10 17 10 4 3 MMU Assist Registers MAS 10 18 10 5 Interrupt Types 10 23 10 6 Bus Interface Unit BIU 10 25 Chapter 11 e200z0 Core Z0 11 1 Introduction 11...

Page 15: ...annel Mux DMA_MUX 13 1 Introduction 13 1 13 1 1 Block Diagram 13 1 13 1 2 Features 13 2 13 1 3 Modes of Operation 13 2 13 2 External Signal Description 13 2 13 3 Memory Map and Registers 13 2 13 3 1 M...

Page 16: ...8 Chapter 16 Miscellaneous Control Module MCM 16 1 Introduction 16 1 16 1 1 Features 16 1 16 2 Memory Map and Registers 16 2 16 2 1 Module Memory Map 16 2 16 2 2 Register Descriptions 16 4 16 3 Functi...

Page 17: ...Diagram 19 1 19 1 2 Features 19 2 19 1 3 Modes of Operation 19 2 19 2 External Signal Description 19 4 19 3 Memory Map and Registers 19 4 19 3 1 Instruction Register 19 4 19 3 2 Bypass Register 19 4...

Page 18: ...ssaging 20 19 20 5 6 EVTO Sharing 20 19 20 5 7 Nexus2 DMA Control 20 19 20 5 8 Debug Mode Control 20 19 20 5 9 Nexus Reset Control 20 22 Chapter 21 Internal Static RAM SRAM 21 1 Introduction 21 1 21 1...

Page 19: ...tion 23 4 23 3 Memory Map and Registers 23 4 23 3 1 Module Memory Map 23 4 23 3 2 Register Descriptions 23 5 23 4 Functional Description 23 29 23 4 1 Modes of Operation 23 30 23 4 2 Start and Stop of...

Page 20: ...24 4 7 Disabling the eSCI 24 30 24 4 8 Interrupt Operation 24 31 24 4 9 Using the LIN Hardware 24 34 Chapter 25 Controller Area Network FlexCAN 25 1 Introduction 25 1 25 1 1 Block Diagram 25 1 25 1 2...

Page 21: ...6 8 26 4 3 eMIOS200 Output Update Disable EMIOS_OUDR 26 8 26 4 4 eMIOS200 Disable Channel EMIOSUCDIS 26 9 26 4 5 eMIOS200 A Register EMIOS_CADR n 26 9 26 4 6 eMIOS200 B Register EMIOS_CBDR n 26 10 26...

Page 22: ...Description 28 3 28 2 1 External Signal Description 28 3 28 3 Memory Map and Registers 28 3 28 3 1 Module Memory Map 28 3 28 3 2 Register Descriptions 28 4 28 4 Functional Description 28 9 28 4 1 Time...

Page 23: ...0 4 Protocol Engine Clocking 30 7 30 4 1 Oscillator Clocking 30 8 30 4 2 PLL Clocking 30 8 30 5 Memory Map and Register Description 30 8 30 5 1 Memory Map 30 8 30 5 2 Register Descriptions 30 11 30 6...

Page 24: ...3 Memory Map and Registers 31 5 31 3 1 Module Memory Map 31 6 31 3 2 Register Descriptions 31 9 31 3 3 eQADC Register Descriptions 31 9 31 3 4 On Chip ADC Registers 31 25 31 4 Functional Description 3...

Page 25: ...cription 32 3 32 3 1 BAM Program Resources 32 3 32 3 2 BAM Program Operation 32 3 32 3 3 Features 32 5 Chapter 33 Media Local Bus MLB 33 1 Introduction 33 1 33 1 1 Block Diagram 33 1 33 1 2 Features 3...

Page 26: ...field numbers is not possible In the Nexus standard register bits are numbered according to the alternative convention LSB 0 As the CPU core on the MPC5510 family cannot access Nexus registers direct...

Page 27: ...oller IMUX Interrupt Requests from Peripheral Blocks DMA Requests from Peripheral Blocks SIU 32 bit 32 bit Mx AXBS Master Port Sx AXBS Slave Port EBI 32 bit S3 S0 M4 M0 M3 M5 M2 M1 Nexus Port JTAG Por...

Page 28: ...Semiconductor 1 3 Preliminary 1 3 MPC5510 Family Comparison Table 1 1 provides a summary of the different members of the MPC5510 family and their proposed features This information is intended to prov...

Page 29: ...eMIOS200 5 IC input capture O C output compare PWM pulse width modulation 24 channels 16 bit 8 channels IC OC 16 channels PWM IC OC Real Time Clock ext 32 KHz Crystal ext 32 KHz Crystal ext 32 KHz Cr...

Page 30: ...at allows users to graphically configure I O to meet the requirements of the peripheral functions More information on this tool can be found at http www freescale com mpc55xx Table 1 2 Flash Memory Sc...

Page 31: ...g a range of 16 bit input capture output compare and pulse width modulation functions eMIOS200 A 12 bit analog to digital converter ADC Up to four serial peripheral interface DSPI modules Media Local...

Page 32: ...he RTC and can be optionally stopped to the oscillator or FMPLL at the expense of a slower start up time STOP is entered from RUN mode On exiting STOP mode the device returns to the RUN mode SLEEP mod...

Page 33: ...llaneous Control Module MCM 0xFFF4_4000 0xFFF4_7FFF 16 K Enhanced Direct Memory Access Controller eDMA 0xFFF4_8000 0xFFF4_BFFF 16 K Interrupt Controller INTC 0xFFF4_C000 0xFFF7_FFFF 208 K Reserved 0xF...

Page 34: ...16 K Controller Area Network FlexCAN_F 0xFFFD_8000 0xFFFD_BFFF 16 K FlexRay Controller FlexRay 0xFFFD_C000 0xFFFD_FFFF 16 K DMA Multiplexer DMA_MUX 0xFFFE_0000 0xFFFE_3FFF 16 K Programmable Interrupt...

Page 35: ...Overview MPC5510 Microcontroller Family Reference Manual Rev 1 1 10 Freescale Semiconductor Preliminary...

Page 36: ...n lists the functions associated with the programming of the SIU_PCRx PA bit in the order general purpose input output GPIO function 1 function 2 and function 3 If fewer than three functions and GPIO...

Page 37: ...Hz Crystal Oscillator Input I I I VDDA AE IH 136 167 D6 PA15 15 PA 15 AN 15 XTAL325 GPI eQADC Analog Input 32 kHz Crystal Oscillator Output I I O VDDA AE IH 135 165 C6 Port B 16 Section Page 2 7 2 2 1...

Page 38: ...el DSPI_B Peripheral Chip Select I O I O O VDDE1 A SH 123 149 B10 PB12 28 PB 12 TXD_G PCS_B 4 GPIO SCI_G Transmit DSPI_B Peripheral Chip Select I O O O VDDE1 SH 164 A7 PB13 29 PB 13 RXD_G PCS_B 3 GPIO...

Page 39: ...35 C13 PC10 42 PC 10 eMIOS 10 PCS_C 5 SCK_D GPIO eMIOS Channel DSPI_C Peripheral Chip Select DSPI_D Clock I O I O O I O VDDE1 SH 110 134 A14 PC11 43 PC 11 eMIOS 11 PCS_C 4 SOUT_D GPIO eMIOS Channel DS...

Page 40: ...TXD_A eMIOS 14 GPIO SCI_A Transmit eMIOS Channel I O O O VDDE1 SH 98 122 F14 PD7 55 PD 7 RXD_A eMIOS 15 GPIO SCI_A Receive eMIOS Channel I O I O VDDE1 SH 97 121 F15 PD8 56 PD 8 TXD_B SCL_A GPIO SCI_B...

Page 41: ...MLBSIG_BUFEN GPIO DSPI_A Clock eMIOS Channel MLB Signal Out 5 pin MLB Signal Level Shifter Enable 3 pin I O I O O O O VDDE1 MH 83 100 M13 PE4 68 PE 4 SOUT_A eMIOS 1 MLBDO MLBDAT_BUFEN GPIO DSPI_A Data...

Page 42: ...Muxed Address Data EBI Non Muxed Address MLB Signal Out 5 pin MLB Signal Level Shifter Enable 3 pin Nexus Message Data Out I O I O O O O O VDDE3 MH 59 74 T10 PF5 85 PF 5 AD 11 ADDR 11 MLBDO MLBDAT_BUF...

Page 43: ...VDDE2 MH 45 55 P6 PF15 95 PF 15 WE 1 TEA CNRX_D GPIO EBI Write Enable EBI Transfer Error Acknowledge CAN_D Receive I O O I O I VDDE2 MH 44 54 N6 Port G 16 Section Page 2 7 7 2 28 PG0 96 PG 0 AD 16 eMI...

Page 44: ...7 PG 11 AD 27 PCS_A 1 GPIO EBI Muxed Address Data DSPI_A Peripheral Chip Select I O I O O VDDE2 MH 29 37 N1 PG12 108 PG 12 AD 28 PCS_A 0 GPIO EBI Muxed Address Data DSPI_A Peripheral Chip Select I O I...

Page 45: ...H 17 22 J1 PH8 120 PH 8 AN 19 CNTX_E MA 0 GPIO eQADC Analog Input6 CAN_E Transmit eQADC External Mux Address I O I O O VDDE2 A SH 14 17 H1 PH9 121 PH 9 AN 18 ANT CNRX_E GPIO eQADC Analog Input6 CAN_E...

Page 46: ...Peripheral Chip Select I O I O VDDE2 SH 19 H3 PJ12 140 PJ 12 PCS_D 0 GPIO DSPI_D Peripheral Chip Select I O I O VDDE2 SH 18 H2 PJ13 141 PJ 13 SCK_D GPIO DSPI_D Clock I O I O VDDE2 SH 16 G4 PJ14 142 P...

Page 47: ...apply on the 144LQFP These functions are on PortK 0 1 for the 176LQFP and 208BGA 6 This analog input pin has reduced analog to digital conversion accuracy compared to PA0 PA15 See the MPC5510 Microco...

Page 48: ...Read Power VDD Internal Logic Power 1 5 V 31 53 79 39 63 95 A1 A16 B2 B15 R2 R15 T1 T16 VDDF Flash Internal Logic Power 79 95 Shorted to VDD in the package VSS Ground 80 96 C3 C14 D4 D13 G7 G10 H7 H10...

Page 49: ...PCS_C1 PB5 AN33 PCS_C0 PB6 AN34 SCK_C PB7 AN35 SOUT_C PB8 AN36 SIN_C PB9 AN37 CNTX_D PCS_B4 PB10 AN38 CNRX_D PCS_B3 PB11 AN39 eMIOS19 PCS_B5 PC0 eMIOS0 FR_A_TX_EN AD24 PC1 eMIOS1 FR_A_TX AD16 PC2 eMI...

Page 50: ...56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 CNTX_D BDIP WE0 PF14 V DDR V SSE2 V DDE2 RXD_D OE PF13 ALE TXD_D TS PF12 MDO7 RXD_C CS0 PF11 MDO6 TXD_C CS1 PF10 MDO5 ADDR15 AD15 PF9...

Page 51: ...PD7 PD9 F PD8 G VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PE8 H VSS VSS VSS VSS PE9 PD14 PE11 PE10 J PE12 PD15 VDDE1 PE0 K PE13 PE1 PE14 L PE3 M VSS VDDE2 PF0 VSS N VSS PG3 PF1 PF3 VSS VPP XTAL...

Page 52: ...MIOS 16 is an output only channel pin for the eMIOS200 module PCS_C 5 is a peripheral chip select output pin for the DSPI C module 2 7 2 2 PB1 GPIO PB 1 Analog Input AN 29 eMIOS Channel eMIOS 17 DSPI_...

Page 53: ...B 9 Analog Input AN 37 CAN_D Transmit CNTX_D DSPI_B Peripheral Chip Select PCS_B 4 PB 9 is a GPIO pin AN 37 is a single ended analog input pin CNTX_D is the transmit pin for the FlexCan D module PCS_B...

Page 54: ...nable pin AD 24 is the external bus interface EBI multiplexed address and data bus 2 7 3 2 PC1 GPIO PC 1 eMIOS Channel eMIOS 1 FlexRay Channel A Transmit FR_A_TX EBI Multiplexed Address Data AD 16 PC...

Page 55: ...annel pin for the eMIOS200 module FR_B_TX is the FlexRay Channel B transmit pin AD 15 is the EBI multiplexed address and data bus 2 7 3 10 PC9 GPIO PC 9 eMIOS Channel eMIOS 9 FlexRay Channel B Transmi...

Page 56: ...lect PCS_A 4 DSPI_D Peripheral Chip Select PCS_D 1 PC 14 is a GPIO pin eMIOS 14 is an input output channel pin for the eMIOS200 module PCS_A 4 is a peripheral chip select output pin for the DSPI A mod...

Page 57: ...e 2 7 4 5 PD4 GPIO PD 4 CAN_C Transmit CNTX_C eMIOS Channel eMIOS 12 PD 4 is a GPIO pin CNTX_C is the transmit pin for the FlexCan C module eMIOS 12 is an output only channel pin for the eMIOS200 modu...

Page 58: ...t output pin for the DSPI B module CNRX_F is the receive pin for the FlexCan F module NMI1 is the critical interrupt input for the e200z0 core 2 7 4 13 PD12 GPIO PD 12 DSPI_B Peripheral Chip Select PC...

Page 59: ...in PCS_A 0 is a peripheral chip select output pin for the DSPI A module eMIOS 3 is an output only channel pin for the eMIOS200 module In a 3 pin MLB interface MLBDAT is the bidirectional data line tha...

Page 60: ...the Nexus Debug port After reset the EVTI pin initiates program and data trace synchronization messages or generates a breakpoint 2 7 6 2 PF1 GPIO PF 1 EBI Transfer Acknowledge TA Nexus Event Out EVTO...

Page 61: ...ated MLB module to the MOST network controller MDO 0 is a trace message output to the development tools 2 7 6 6 PF5 GPIO PF 5 EBI Multiplex Address Data AD 11 EBI Non Muxed Address ADDR 11 MLB Data Ou...

Page 62: ...Data Out MDO 7 PF 11 is a GPIO pin CS 0 is the EBI chip select output signals RXD_C is the receive pin for the eSCI C module MDO 7 is a trace message output to the development tools 2 7 6 13 PF12 GPI...

Page 63: ...the data output pin for the DSPI C module 2 7 7 4 PG3 GPIO PG 3 EBI Multiplex Address Data AD 19 eMIOS Channel eMIOS 19 DSPI_C Serial Clock SCK_C PG 3 is a GPIO pin AD 19 is the EBI multiplexed addre...

Page 64: ...module 2 7 7 11 PG10 GPIO PG 10 EBI Multiplex Address Data AD 26 DSPI_A Peripheral Chip Select PCS_A 2 PG 10 is a GPIO pin AD 26 is the EBI multiplexed address and data bus PCS_A 2 is a peripheral chi...

Page 65: ...g Input AN 25 eMIOS Channel eMIOS 22 EBI Chip Select CS 3 PH 2 is a GPIO pin AN 25 is a single ended analog input pin eMIOS 22 is an output only channel pin for the eMIOS200 module CS 3 is an EBI chip...

Page 66: ...o select the mux input channel to connect to the QADC 2 7 8 10 PH9 GPIO PH 9 Analog Input AN 18 CAN_E Receive CNRX_E PH 9 is a GPIO pin AN 18 is a single ended analog input pin CNRX_E is the receive p...

Page 67: ...heral chip select output pin for the DSPI_D module 2 7 9 4 PJ10 GPIO PJ10 DSPI_D Peripheral Chip Select PCS_D 2 PJ10 is a GPIO pin PCS_D 2 is a peripheral chip select output pin for the DSPI_D module...

Page 68: ...an external crystal oscillator 2 7 11 2 EXTAL Crystal Oscillator Input External Clock Input EXTAL is the input pin for an external crystal oscillator or an external clock source The alternate functio...

Page 69: ...2 VDDA Analog to Digital Converter Analog Supply VDDA is the analog supply for the eQADC 2 7 12 3 VSSA Analog to Digital Converter Analog Ground VSSA is the analog ground for the eQADC 2 7 12 4 VRH An...

Page 70: ...ly 2 7 12 10 VPP Flash Program Erase Supply VPP is the on chip flash program erase supply 2 7 12 11 VDD Internal Logic Supply and Flash Logic Supply VDDF VDD is the 1 5 V logic and flash supply 2 7 12...

Page 71: ...Signal Descriptions MPC5510 Microcontroller Family Reference Manual Rev 1 2 36 Freescale Semiconductor Preliminary...

Page 72: ...clock may be generated in several ways Internal 16 MHz IRC PLL Normal mode with crystal clock reference for XOSC PLL Normal mode with external clock reference for XOSC XOSC with external clock refere...

Page 73: ...square wave input can also be supplied to the device through the oscillator by connecting the external clock source to the EXTAL pin with the oscillator operating in external clock mode Features Supp...

Page 74: ...clock the RTC to provide accurate time keeping Powered from 5 V Optional disable 3 2 3 Internal High Frequency RC Oscillator IRC The MPC5510 includes a 16 MHz IRC as the default system clock out of r...

Page 75: ...level halt mechanism Figure 3 2 shows the device level clock gating mechanism for the MPC5510 These features are detailed in subsequent sections Figure 3 2 System Clock Architecture PLL IRC Switcher...

Page 76: ...quency The EBI supports gating of the CLKOUT signal when there are no external bus accesses in progress The CLKOUT divider provides a nominal 50 duty cycle clock There is no guaranteed phase relations...

Page 77: ...th other basic module functions such as interrupts DMA etc 3 5 Software Controlled Power Management 3 5 1 Module Disable MDIS Clock Gating Static clock gating is enabled by software writes to configur...

Page 78: ...be stopped Then software sets the HLT bits for the eDMA and FlexRay to indicate to the clock logic that the clocks to these modules can now be stopped When the HLT bits for the eDMA and FlexRay are se...

Page 79: ...when switching of the system clock or the CAN protocol engine clock source or before the desired clock source has stabilized the FlexCAN module must first be disabled by setting the FlexCAN_x_MCR MDI...

Page 80: ...Hz IRC the 32 kHz OSC or the 16 MHz IRC NOTE To prevent improper real time clock RTC behavior when switching the system clock source or before the desired clock source has stabilized the RTC must firs...

Page 81: ...System Clock Description MPC5510 Microcontroller Family Reference Manual Rev 1 3 10 Freescale Semiconductor Preliminary...

Page 82: ...fferent owing to the use of an internal 16 MHz IRC low power modes and other features specific to the 5510 family 4 1 1 Block Diagram A simplified block diagram of the FMPLL illustrates the functional...

Page 83: ...rence and FMPLL output clocks with programmable ability to select a backup clock source as well as generate a reset or interrupt in the event of a failure 4 1 3 Modes of Operation There are two main m...

Page 84: ..._0000 Register Access Reset Value Section Page 0x0000 Reserved 0x0004 SYNSR FMPLL Synthesizer Status Register R W 1 1 See specific register description 4 3 2 1 4 3 0x0008 ESYNCR1 FMPLL Enhanced Synthe...

Page 85: ...l be reflected in this location 1 PLL clock mode 0 PLL Off mode PLLSEL PLL Mode Select The initial value for the PLLSEL bit is determined at reset The state of this bit along with MODE and PLLREF indi...

Page 86: ...t A loss of clock condition can only be detected if LOCEN 1 1 Interrupt service requested 0 Interrupt service not requested CALDONE Calibration Complete The CALDONE bit is an indication of whether the...

Page 87: ...YNCR2 LOLRE and ESYNCR2 LOCRE should be set to 0 before changing the PLL mode so that a reset is not immediately generated upon the write to CLKCFG 0 2 bits 4 11 Reserved EPREDIV Enhanced Pre Divider...

Page 88: ...be within the fvco specification see MPC5510 data sheet When the EMFD bits are changed the PLL loses lock If the EMFD bits are changed during FM calibration the current calibration sequence is termin...

Page 89: ...4 FMPLL Enhanced Synthesizer Control Register 2 ESYNCR2 Table 4 7 ESYNCR2 Field Descriptions Field Description bits 0 7 Reserved LOCEN Loss of Clock Enable The LOCEN bit determines whether the loss of...

Page 90: ...on applied to the system frequency Table 4 8 shows the allowable modulation rates bits 16 20 Reserved EDEPTH Enhanced Modulation Depth The EDEPTH bit field controls the frequency modulation depth and...

Page 91: ...al 40 10 Fmod Fextal 20 11 Invalid Table 4 9 Programmable Modulation Depths EDEPTH Modulation Depth of Fsys 000 0 001 0 25 0 5 010 0 75 1 0 011 1 25 1 5 100 1 75 2 0 101 111 Reserved Table 4 10 Enhanc...

Page 92: ...is off and either the 16 MHz IRC must be selected as the system clock or the user must supply an external clock or crystal on the EXTAL pin and select that clock source before entering PLL Off mode Th...

Page 93: ...and the lock detect process is repeated The alternate count sequences prevent false lock detects due to frequency aliasing while the PLL tries to lock Alternating between a tight and relaxed lock crit...

Page 94: ...hich clock source has failed the LOC circuitry switches the PLL s output clock source to the remaining operational clock if enabled by LOCEN The PLL s output clocks are derived from the alternate cloc...

Page 95: ...ck leads the falling edge of the feedback clock then the UP signal is pulsed If the falling edge of the feedback clock leads the falling edge of the reference clock then the DOWN signal is pulsed The...

Page 96: ...nd EMFD range 2 Write a value of ERFD ERFD from step 1 1 to the ERFD field of the ESYNCR2 Not increasing the ERFD when changing the EPREDIV or EMFD could subject the device to clock frequencies beyond...

Page 97: ...kes place error incurred will not be corrected The calibration system reuses the two counters in the lock detect circuit the reference and feedback counters The reference counter remains clocked by th...

Page 98: ...uccessfully CALPASS is set to 1 4 4 3 4 2 Programming System Clock Frequency With Frequency Modulation The following steps illustrate proper programming of the frequency modulation mode These steps en...

Page 99: ...ate in self clocked mode SCM until a valid reference clock is detected by the internal clock monitor circuit Internal to the PLL the VCO will be held in reset until the negation of the POR signal This...

Page 100: ...ondition occurred In PLL Off mode the PLL cannot lock therefore a loss of lock condition cannot occur and LOLRE has no affect 4 5 3 PLL Loss of Clock Reset When a loss of clock condition is recognized...

Page 101: ...Frequency Modulated Phase Locked Loop FMPLL MPC5510 Microcontroller Family Reference Manual Rev 1 4 20 Freescale Semiconductor Preliminary...

Page 102: ...be driven to known states when the logic driving the input is powered down The RTC API block implements a real time counter and periodic interrupt The wakeup and power status block implements the logi...

Page 103: ...Semiconductor Preliminary Figure 5 1 CRP Block Diagram RTC LOW BIU POWER FSM API CLOCKS RESET CONTROL WAKEUP POWER STATUS SEA OF GATES LOGIC 16MIRC 32KIRC 32KXOSC CONTROL CLOCK BLOCK VREG XOSC RAM BL...

Page 104: ...oth sleep and stop modes FSM clock gates itself off when waiting for asynchronous wakeup signal for power savings Eight selections available for blocks sizes for RAM data retention Low power wakeup Wa...

Page 105: ...order and describes the registers and their bit fields Table 5 1 CRP Memory Map Offset from CRP_BASE 0xFFFE_C000 Register Access Reset Value Section Page 0x0000 CRP_CLKSRC Clock Source Register R W 0...

Page 106: ...N LVI VDD5 Low LVI and VDD5 LVI 2 These bits must not be changed 3 These bits must remain set to a value of 1 Only the six least significant bits of TRIM32IRC are used Figure 5 2 Clock Source Register...

Page 107: ...bits control the 16 MHz IRC internal reference clock frequency by controlling the internal reference clock period The bits effect are binary weighted i e bit 6 adjusts twice as much as bit 7 Increasin...

Page 108: ...0 to ROVRF has no effect Note that the ROVRF bit must be cleared before entering SLEEP or STOP mode if the RTC rollover is to be used as the wakeup source 0 RTC has not rolled over 1 RTC has rolled ov...

Page 109: ...may only be updated when APIEN is 0 or API function is undefined Note The compare value will be the number in the API 1 Numbers less than 3 should not be used as synchronization requires up to 2 clock...

Page 110: ...urces see Table 5 6 Table 5 6 Wakeup Source Selects 111 110 101 100 011 010 001 000 WKPSEL0 PG11 PD15 PD10 PD0 PC2 PB13 PA4 PA0 WKPSEL1 PJ12 PG15 PD14 PD13 PC4 PB15 PA5 PA1 WKPSEL2 PF10 PD6 PD1 PC0 PB...

Page 111: ...exit from low power modes 0 RTC rollover will not generate a wakeup request from low power mode 1 RTC rollover will generate a wakeup request from low power modes RTCWKEN RTC Wakeup Enable The RTCWKE...

Page 112: ...ble 5 8 CRP_Z1VEC Field Descriptions Field Description Z1VEC Z1 Recovery Vector The Z1VEC value determines the initial program counter for the Z1 upon exiting reset On POR the value contained in the r...

Page 113: ...on negation of the Z0RST bit or to a location for the Z0 to start running code when exiting Low Power modes if it was not in RESET before entering the low power mode Z0RST Controls the assertion of RE...

Page 114: ...sleep mode points to a memory other than the flash This allows code to be executed from those other memories while the flash completes its internal initialization 0 Reset occurs for 2400 or 9600 clock...

Page 115: ...e interrupt flag and a write of 0 has no effect 0 The RTC did not cause the last wakeup 1 The RTC caused the last wakeup PWKSRCF Pin Wakeup Source Flag The PWKSRCF bits indicate which external pin wak...

Page 116: ...00_7FFF 110 64K RAM retains power 0x4000_0000 0x4000_FFFF 111 80K RAM retains power 0x4000_0000 0x4001_3FFF Other reserved defaults to 80K on MPC5510 PWKSRIE 0 7 Pin Wakeup Source Interrupt Enable The...

Page 117: ...0 LVI5 interrupts disabled 1 LVI5 interrupts enabled LVI5HIE LVI5 High Interrupt Enable TheLVI5HIE bit enables interrupts requests to the system if LVI5HF is asserted 0 LVI5H interrupts disabled 1 LVI...

Page 118: ...prior to disabling the PLL or powering down the XOSC The PLL should then be disabled since it does not clock any logic in sleep or stop modes The main external oscillator XOSC can be optionally powere...

Page 119: ...e CRP_PSCR register determine the amount of RAM that remains powered in sleep mode This selection must be made prior to executing the WAIT instructions to the cores with the CRP_PSCR SLEEP bit set 5 3...

Page 120: ...iagram Run Mode Mode Transition RUN SLEEP STOP INIT T F F F F F T T T T Sleep or Stop debug enabled Set Sleep Stop Handshake bit in NPC PCR Handshake bit cleared Acknowledge clock stop ready to CCB Cl...

Page 121: ...wakeup edge if 16MIRC enabled depends on where pin wakeup edge occurred 3 clks 16MIRC start up time if disabled SLEEP RUN wait 5 usec Negate PMC run Disable LVI Assert FSM sleep flag Assert PMC run A...

Page 122: ...art clocks firewall 19 Debug Enabled Block NPC debug signals dbg clk 16MIRC Assert core debug enable Assert pad keeper data select pre release T F wait core debug ack 17a 17b 17c Negate core debug ena...

Page 123: ...eeper SOG vss source pre driver PwrGate firewall Enable LVIs 8 9 10 11 12 4 5 6 7 1 2 3 Mode Transition PwrGate switch open switch open wakeup 1 wait 5 usec Assert prerun SOG vss source pre driver Pwr...

Page 124: ...outputs in the SIU PCR registers Pins that are to be used for wakeup from sleep stop modes must have the IBE enabled in the SIU PCR prior to sleep stop entry If a pullup down is enabled on an input pi...

Page 125: ...the reset controller sequence completes The CRP_PSCR SLEEPF bit will be set in this case to indicate that the POR came from a sleep recovery Note that when powering up from sleep mode the BOOTCFG pin...

Page 126: ...a CAN receive pin to wake up the device on a transition For example WKPSEL7 could select PF15 which could be assigned to CNRX_D The corresponding CRP_PSCR PWKSRCF flag bit will be set when a selected...

Page 127: ...he pad keepers are released immediately on wakeup from STOP mode Any debug functionality that was enabled prior to STOP mode will be enabled after waking up from STOP mode On exit from STOP mode after...

Page 128: ...e Nexus pins cannot be used until the NPC configuration is restored The TDO pin remains asserted until the debug tool sets the SLEEP_SYNC bit in the NPC PCR register At that point TDO is negated contr...

Page 129: ...or sleep mode when the RTC interval is reached the RTC will first generate a wakeup and then assert the interrupt request The RTC also supports an autonomous periodic interrupt function used to gener...

Page 130: ...free running counter enabled with CNTEN CNTEN when negated asynchronously resets the counter and synchronously enables the counter when enabled The value of the counter may be read via the RTCCNT regi...

Page 131: ...upt function The 10 bit APIVAL selects the time interval for triggering an interrupt and or wakeup event Since the RTC is a free running counter the APIVAL is added to the current count to calculate a...

Page 132: ...e use of the RTC are as follows RTC status and control register Section 5 2 2 2 RTC Status and Control Register CRP_RTCSC RTC counter register Section 5 2 2 3 RTC Counter Register CRP_RTCCNT 0 1 2 CLK...

Page 133: ...4 0V LVI5H 5 V VDDA supply generate interrupt if the 5 V VREG output is out of limit nominal 4 8 V The LVI15 LVI33 LVI33SYN and LVI5L only generate resets The reset request will cause a system reset a...

Page 134: ...to be partially functional The supply ramp is assumed to be relatively slow Thus the CRP_SOCSC LVI5HF is used as an early interrupt warning indication that the supply voltage is falling Based on the L...

Page 135: ...Clock Reset and Power Control CRP MPC5510 Microcontroller Family Reference Manual Rev 1 5 34 Freescale Semiconductor Preliminary...

Page 136: ...ck contains the external pin boot configuration logic The pad configuration block controls the static electrical characteristics of I O pins The GPIO block provides uniform and discrete input output c...

Page 137: ...owing System configuration MCU reset configuration via external pins Pad configuration control Reset RESET Configuration SIU Registers Reset Controller Pad Interface Pad Ring Pad Configuration Power o...

Page 138: ...en read using dedicated input output registers Internal multiplexing Allows flexible selection of eQADC trigger inputs Allows selection of interrupt requests among external pins Allows selection of eM...

Page 139: ...utput SIU_GPDO register controls each GPIO input and output separately See Section 6 3 2 14 GPIO Pin Data Output Registers SIU_GPDO16_19 SIU_GPDO140_143 Section 6 3 2 15 GPIO Pin Data Input Registers...

Page 140: ...16 0x0020 0x0023 SIU_OSR Overrun Status Register R W 0x0000_0000 6 3 2 7 6 17 0x0024 0x0027 SIU_ORER Overrun Request Enable Register R W 0x0000_0000 6 3 2 8 6 18 0x0028 0x002B SIU_IREER External IRQ R...

Page 141: ...Request R W 0x0000_0000 6 3 2 26 6 38 0x09A8 0x09AB SIU_HLTACK Halt Acknowledge R 0x0000_0000 6 3 2 27 6 39 0x09AC 0x0BFF Reserved 0x0C00 0x0C13 SIU_PGPDO0 SIU_PGPDO4 Parallel GPIO Pin Data Output Reg...

Page 142: ...613 FFFE8813 PB4 20 FFFE8068 FFFE8614 FFFE8814 PB5 21 FFFE806A FFFE8615 FFFE8815 PB6 22 FFFE806C FFFE8616 FFFE8816 PB7 23 FFFE806E FFFE8617 FFFE8817 PB8 24 FFFE8070 FFFE8618 FFFE8818 PB9 25 FFFE8072 F...

Page 143: ...50 FFFE80A4 FFFE8632 FFFE8832 PD3 51 FFFE80A6 FFFE8633 FFFE8833 PD4 52 FFFE80A8 FFFE8634 FFFE8834 PD5 53 FFFE80AA FFFE8635 FFFE8835 PD6 54 FFFE80AC FFFE8636 FFFE8836 PD7 55 FFFE80AE FFFE8637 FFFE8837...

Page 144: ...82 FFFE80E4 FFFE8652 FFFE8852 PF3 83 FFFE80E6 FFFE8653 FFFE8853 PF4 84 FFFE80E8 FFFE8654 FFFE8854 PF5 85 FFFE80EA FFFE8655 FFFE8855 PF6 86 FFFE80EC FFFE8656 FFFE8856 PF7 87 FFFE80EE FFFE8657 FFFE8857...

Page 145: ...4 FFFE8124 FFFE8672 FFFE8872 PH3 115 FFFE8126 FFFE8673 FFFE8873 PH4 116 FFFE8128 FFFE8674 FFFE8874 PH5 117 FFFE812A FFFE8675 FFFE8875 PH6 118 FFFE812C FFFE8676 FFFE8876 PH7 119 FFFE812E FFFE8677 FFFE8...

Page 146: ...vice s specific mask revision level PJ5 133 FFFE814A FFFE8685 FFFE8885 PJ6 134 FFFE814C FFFE8686 FFFE8886 PJ7 135 FFFE814E FFFE8687 FFFE8887 PJ8 136 FFFE8150 FFFE8688 FFFE8888 PJ9 137 FFFE8152 FFFE868...

Page 147: ...oritized When reset requests of different priorities occur on the same clock cycle the lower priority reset request is ignored Only the highest priority reset request s status bit is set Except for a...

Page 148: ...able 6 5 SIU_RSR Field Descriptions Field Description PORS Power on Reset Status Also set upon recover from sleep mode 0 The reset controller acknowledged another reset source since the last assertion...

Page 149: ...0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CRE0 CRE1 0 0 0 0 0 0 SSRL3 0 0 0 0 0 0 0 W Reset 12 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 The S...

Page 150: ...n the e200z1 checkstop reset input to the reset controller is asserted CRE1 Checkstop Reset Enable enable secondary CPU Z0 checkstop to generate reset Writing a 1 to this bit enables a reset when the...

Page 151: ...lag for primary CPU Z1 or secondary CPU Z0 NMI0 is for the primary core NMI1 is for the secondary core This bit is set when an edge triggered event occurs on the corresponding NMIn input 0 No edge tri...

Page 152: ...Select Register SIU_DIRSR Table 6 9 SIU_DIRER Field Descriptions Field Description bits 0 26 Reserved DIRSn DMA Interrupt Request Select n Selects between a DMA or interrupt request when an edge trig...

Page 153: ...SR Field Descriptions Field Function bits 0 15 Reserved OVFn Overrun Flag n This bit is set when an overrun occurs on the corresponding IRQn pin 0 No overrun occurred on the corresponding IRQn pin 1 A...

Page 154: ...0 0 0 0 0 0 0 0 Figure 6 10 IRQ Rising Edge Event Enable Register SIU_IREER Table 6 12 SIU_IREER Field Descriptions Field Function NREEn NREEn NMI Rising Edge Event Enable n These write once bits enab...

Page 155: ...ing NMIn input 0 Falling edge event disabled 1 Falling edge event enabled bits 2 15 Reserved IFEEn IRQ Falling Edge Event Enable n Enables falling edge triggered events on the corresponding IRQn pin 0...

Page 156: ...st be set accordingly IBE 1 for input and OBE 1 for output For I O functions that change direction dynamically such as the external data bus switching between input and output is handled internally an...

Page 157: ...iated parallel port name and associated bit number For example the Port A pins are named PA0 to PA15 these pin names should not be confused with the bit field name See Chapter 2 Signal Descriptions fo...

Page 158: ...medium I O pad types and the output signals are driven according to the value of this field Actual slew rate is dependent on the pad type and load See the MPC5510 Microcontroller Family Data Sheet fo...

Page 159: ...h one bit per byte Each of the 128 PDO bits corresponds to a port pin in the order given in Table 6 18 Gaps exist in this memory space where the pin is not available in the package NOTE On MPC5510 the...

Page 160: ...Field Descriptions Field Description PDOn Pin Data Out Stores the data to be driven out on the external GPIO pin associated with the register If the register is read it returns the value written 0 VO...

Page 161: ...IU_GPDIx_x register reflects the actual state of the output pin 96_99 100_103 104_107 108_111 0x0660 0x0664 0x0668 0x066C PG0 PG3 PG4 PG7 PG8 PG11 PG12 PG15 112_115 116_119 120_123 124_127 0x0670 0x06...

Page 162: ...PB8 PB11 PB12 PB15 32_35 36_39 40_43 44_47 0x0820 0x0824 0x0828 0x082C PC0 PC3 PC4 PC7 PC8 PC11 PC12 PC15 48_51 52_55 56_59 60_63 0x0830 0x0834 0x0838 0x083C PD0 PD3 PD4 PD7 PD8 PD11 PD12 PD15 64_67 6...

Page 163: ...11 12 13 14 15 R TSEL3 TSEL2 TSEL1 TSEL0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0...

Page 164: ...6 20 IMUX Select Register 1 SIU_ISEL1 Table 6 22 SIU_ISEL1 Field Descriptions Field Description1 ESEL15 External IRQ Input Select 15 Specifies input for IRQ15 00 PD4 01 PF15 10 PG14 11 PH6 ESEL14 Exte...

Page 165: ...for IRQ7 00 PB14 01 PD7 10 PG6 11 PC5 ESEL6 External IRQ Input Select 6 Specifies input for IRQ6 00 PA6 01 PB8 10 PD1 11 PF10 ESEL5 External IRQ Input Select 5 Specifies input for IRQ5 00 PA5 01 PB15...

Page 166: ...ccess User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R SELEMIOS 15 SELEMIOS 14 SELEMIOS 13 SELEMIOS 12 SELEMIOS 11 SELEMIOS 10 SELEMIOS 9 SELEMIOS 8 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 1...

Page 167: ...g to the SELEMIOS10 field 00 eMIOS 10 input pin 01 DSPI_A deserialized output 10 DSPI_B deserialized output 11 DSPI_C deserialized output SELEMIOS9 eMIOS 9 Input Select The source of the input for the...

Page 168: ...SELEMIOS3 field 00 eMIOS 3 input pin 01 DSPI_A deserialized output 10 DSPI_B deserialized output 11 DSPI_C deserialized output SELEMIOS2 eMIOS 2 Input Select The source of the input for the eMIOS 2 t...

Page 169: ...U The match input is asserted if the values in the SIU_CMPAH SIU_CMPAL and SIU_CMPBH SIU_CMPBL are equal 0 Match input signal is negated 1 Match input signal is asserted DISNEX Disable Nexus The DISNE...

Page 170: ...5 SIU_ECCR Field Descriptions Field Description bits 0 29 Reserved Note Reserved bits 16 24 and 28 are writeable but writing to these bits has no effect other than to update the value of the register...

Page 171: ...cess User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CMPAH W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CMPAH W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 172: ...which peripherals are associated with which LPCLKDIV bit on MPC5510 see Section 3 4 5 Peripheral Clock Dividers Offset SIU_BASE 0x0994 Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CMP...

Page 173: ...is required in addition to the RFD to allow the other sources for the system clock 16 MHz IRC and OSC to be divided to slowest frequencies to improve power 00 Divide by 1 01 Divide by 2 10 Divide by 4...

Page 174: ...31 R HLT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6 29 Halt Register SIU_HLT Table 6 28 HALT Register Field Descriptions Field Description HLT Halt Selects The HL...

Page 175: ...30 31 R HLTACK W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6 30 Halt Acknowledge Register SIU_HLTACK Table 6 29 HLTACK Register Field Descriptions Field Description...

Page 176: ...llel GPIO Pin Data Output Register 2 SIU_PGPDO2 The SIU_PGPDO2 register contains the Parallel GPIO Pin Data Output for PE0 PE15 and PF0 PF15 Reads and writes to this register are coherent with the reg...

Page 177: ...is register are coherent with the registers SIU_GPDO18_131 SIU_GPDO132_135 SIU_GPDO136_139 and SIU_GPDO140_143 NOTE On MPC5510 the port K pins are only inputs Therefore there are no parallel GPIO pin...

Page 178: ...d PD0 PD15 Writes have no effect Reads of this register are coherent with the registers SIU_GPDI32_35 SIU_GPDI36_39 SIU_GPDI40_43 SIU_GPDI44_47 SIU_GPDI48_51 SIU_GPDI52_55 SIU_GPDI56_59 and SIU_GPDI60...

Page 179: ...PG15 and PH0 PH15 Writes have no effect Reads of this register are coherent with the registers SIU_GPDI96_99 SIU_GPDI100_103 SIU_GPDI104_107 SIU_GPDI108_111 SIU_GPDI112_115 SIU_GPDI116_119 SIU_GPDI12...

Page 180: ...it is set For example if the current state of the port B parallel GPIO pin data output register is 0x1234 and you want to change only bits 12 15 i e the 4 to be an 8 then a 32 bit write with a mask va...

Page 181: ...0 15 Writes to this register are coherent with the registers SIU_GPDO48_51 SIU_GPDO52_55 SIU_GPDO56_59 and SIU_GPDO60_63 Offset SIU_BASE 0x0C84 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 1...

Page 182: ...IU_GPDO80_83 SIU_GPDO84_87 SIU_GPDO88_91 and SIU_GPDO92_95 Offset SIU_BASE 0x0C8C Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W PD_MASK 0 15 Reset 0...

Page 183: ...U_GPDO112_115 SIU_GPDO116_119 SIU_GPDO120_123 and SIU_GPDO124_127 Offset SIU_BASE 0x0C94 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W PF_MASK 0 15 R...

Page 184: ...d and whether to initiate a CAN or SCI boot See Section 32 3 3 1 1 Reset Configuration Halfword Read of the BAM chapter for detail on the RCHW Table 6 30 defines the boot modes specified by the SIU_RS...

Page 185: ...roller or a DMA transfer request to the DMA controller The flag bit for IRQ0 can generate an interrupt request if SIU_DIRSR 31 is 0 or is disabled if SIU_DIRSR 0 is 1 Figure 6 49 shows the DMA and int...

Page 186: ...Registers SIU_ISELx provide selection of the input source for the eQADC external trigger inputs and the SIU external interrupts 6 4 5 1 eQADC External Trigger Input Multiplexing The four eQADC extern...

Page 187: ...nput source for each SIU external interrupt is individually specified in the IMUX Select Register 1 SIU_ISEL1 Figure 6 51 shows an example of the multiplexing of an SIU external interrupt input As sho...

Page 188: ...CU is clocked by the 16 MHz IRC clock after any reset The reset status register SIU_RSR gives the source or sources of the last reset and is updated for all reset sources except JTAG reset The BOOTCFG...

Page 189: ...name PD2 in package diagrams and signal lists is used to determine the boot mode initiated by the BAM program The pin state during reset is latched in the SIU_RSR BOOTCFG field The BAM program uses th...

Page 190: ...cleared 7 3 2 4 Loss of Lock Reset A loss of lock reset occurs when the PLL loses lock and the loss of lock reset enable LOLRE bit in the PLL enhanced synthesizer control register 2 ESYNCR2 is set Th...

Page 191: ...The reset state of the system is All pads on ports A K are placed in a disabled mode with output enables input enables and pull devices all disabled except PD2 TDI pad is an input with pullup enabled...

Page 192: ...ual Rev 1 Freescale Semiconductor 7 5 Preliminary Figure 7 1 Reset Configuration Timing RESET VDD POR BOOTCFG is latched 4 clock cycles 2400 clocks BOOTCFG can be applied but not latched User drives c...

Page 193: ...Reset MPC5510 Microcontroller Family Reference Manual Rev 1 7 6 Freescale Semiconductor Preliminary...

Page 194: ...e has envisioned its use INTC has two independent interrupt request outputs one for each core Implies two sets of priority selection vector encoding priority level FIFOs etc Priority level configurati...

Page 195: ...1 Non maskable interrupt pins PD 10 PD 11 Machine Check IVOR 1 0x010 ME CSRR 0 1 ISI ITLB error on first instruction of exception handler Data Storage IVOR 2 0x020 SRR 0 1 Incorrect privilege mode for...

Page 196: ...from the IVPR The vectors for each source are shown in Table 8 2 The Data TLB Error4 IVOR 13 0x0D0 SRR 0 1 Data TLB miss in MMU Instruction TLB Error4 IVOR 14 0x0E0 SRR 0 1 Instruction TLB miss in MM...

Page 197: ...the e200z1 and e200z0 cores respectively See Section 8 4 3 Non Maskable Interrupt NMI for more details on the usage and configuration of the critical interrupt input to the core as a pseudo non maskab...

Page 198: ..._CLR1 0x0804 1 INTC INTC_SSCIR0_3 CLR1 INTC software settable clear flag 1 INTC_SSCIR0_3_CLR2 0x0808 2 INTC INTC_SSCIR0_3 CLR2 INTC software settable clear flag 2 INTC_SSCIR0_3_CLR3 0x080C 3 INTC INTC...

Page 199: ...eDMA DMAINTL INT10 eDMA channel interrupt 10 eDMA_INTL_INT11 0x0858 22 eDMA DMAINTL INT11 eDMA channel interrupt 11 eDMA_INTL_INT12 0x085C 23 eDMA DMAINTL INT12 eDMA channel interrupt 12 eDMA_INTL_IN...

Page 200: ...external interrupt flag 2 SIU_EISR_EIF3 0x08E0 56 SIU SIU_EISR EIF3 SIU external interrupt flag 3 SIU_EISR_EIF15_4 0x08E4 57 SIU SIU_EISR EIF15 EIF4 SIU external interrupt flags 15 4 eMIOS200_FLAG_F0...

Page 201: ...command FIFO underflow interrupt requests from all of the FIFOs eQADC_FISR0_NCF0 0x094C 83 eQADC eQADC_FISR0 NCF0 eQADC command FIFO 0 non coherency flag eQADC_FISR0_PF0 0x0950 84 eQADC eQADC_FISR0 PF...

Page 202: ...SR5 NCF5 eQADC command FIFO 5 non coherency flag eQADC_FISR5_PF5 0x09B4 109 eQADC eQADC_FISR5 PF5 eQADC command FIFO 5 pause flag eQADC_FISR5_EOQF5 0x09B8 110 eQADC eQADC_FISR5 EOQF5 eQADC command FIF...

Page 203: ...AT2 OVFL SCI_C combined interrupt request of the SCI status register 1 transmit data register empty transmit complete receive data register full idle line overrun noise frame error and parity error in...

Page 204: ...A receive warning interrupt FLEXCAN_A_ESR_ERR_INT 0x0A00 128 FLEXCAN_A ESR ERR_INT FLEXCAN_A error interrupt Reserved 0x0A04 129 Reserved Reserved FLEXCAN_A_IFLAG1_BUF0I 0x0A08 130 FLEXCAN_A IFLAG1 BU...

Page 205: ..._INT FLEXCAN_B ESR RWRN_INT FLEXCAN_B bus off interrupt FLEXCAN_B transmit warning interrupt FLEXCAN_B receive warning interrupt FLEXCAN_B_ESR_ERR_INT 0x0A78 158 FLEXCAN_B ESR ERR_INT FLEXCAN_B error...

Page 206: ...interrupt FLEXCAN_C_IFLAG1_BUF5I 0x0AE8 186 FLEXCAN_C IFLAG1 BUF5I FLEXCAN_C buffer 5 interrupt FLEXCAN_C_IFLAG1_BUF6I 0x0AEC 187 FLEXCAN_C IFLAG1 BUF6I FLEXCAN_C buffer 6 interrupt FLEXCAN_C_IFLAG1_...

Page 207: ...XCAN_D IFLAG1 BUF12I FLEXCAN_D buffer 12 interrupt FLEXCAN_D_IFLAG1_BUF13I 0x0B5C 215 FLEXCAN_D IFLAG1 BUF13I FLEXCAN_D buffer 13 interrupt FLEXCAN_D_IFLAG1_BUF14I 0x0B60 216 FLEXCAN_D IFLAG1 BUF14I F...

Page 208: ...ransmit warning interrupt FLEXCAN_F receive warning interrupt FLEXCAN_F_ESR_ERR_INT 0x0BC8 242 FLEXCAN_F ESR ERR_INT FLEXCAN_F error interrupt Reserved 0x0BCC 243 Reserved Reserved FLEXCAN_F_IFLAG1_BU...

Page 209: ..._E_COMB 0x0C38 270 SCI_E SCISR1 TDRE SCI_E SCISR1 TC SCI_E SCISR1 RDRF SCI_E SCISR1 IDLE SCI_E SCISR1 OR SCI_E SCISR1 NF SCI_E SCISR1 FE SCI_E SCISR1 PF SCI_E SCISR2 BERR SCI_E LINSTAT1 RXRDY SCI_E LI...

Page 210: ...AT2 OVFL SCI_G combined interrupt request of the SCI status register 1 transmit data register empty transmit complete receive data register full idle line overrun noise frame error and parity error in...

Page 211: ...DSPI_D DSPI_ISR RFDF DSPI_D Receive FIFO Drain flag FlexRay_GLOB 0x0C70 284 FLEXRAY CIFRR 7 Global FlexRay module interrupt flag FlexRay_PRIF 0x0C74 285 FLEXRAY CIFRR 6 FlexRay protocol status and er...

Page 212: ...R does not need to be read to acknowledge the interrupt request before the e200z1 0 is enabled again to recognize the external input As in software vector mode the timing relationship between popping...

Page 213: ...high priority elevation on critical interrupt events the MCM generates the high priority signal upon critical interrupt detection and holds it active for the duration of interrupt servicing until a re...

Page 214: ...e This bit enables the dynamic elevation of the processor s system bus arbitration priority during critical interrupt processing If set this bit enables the elevated arbitration priority during the ti...

Page 215: ...Interrupts MPC5510 Microcontroller Family Reference Manual Rev 1 8 22 Freescale Semiconductor Preliminary...

Page 216: ...source need to be supported The INTC supports the priority ceiling protocol for coherent accesses By providing a modifiable priority mask the priority can be raised temporarily so that all tasks which...

Page 217: ...o processor ISR at a higher priority preempts ISRs or tasks at lower priorities Automatic pushing or popping of preempted priority to or from a LIFO Ability to modify the ISR or task priority modifyin...

Page 218: ...nterrupt Acknowledge Register Processor 1 End of Interrupt Register Processor 0 End of Interrupt Register 1 Processor 1 Interrupt Vector 9 294 Interrupt Vector 9 Request Selector Priority Arbitrator H...

Page 219: ...handling the interrupt request to the processor to be specific to that vector Therefore the interrupt exception handler is specific to a peripheral or software settable interrupt request rather than b...

Page 220: ...ess the clock reset and power module CRP supports that interrupt request as a wakeup source 9 2 Signal Description The INTC has no external signals 9 3 Memory Map and Registers 9 3 1 Module Memory Map...

Page 221: ...gister INTC_MCR The module configuration register is used to configure options of the INTC 0x0020 0x0024 INTC_SSCIR0_3 INTC software set clear interrupt register 0 3 INTC_SSCIR4_7 INTC software set cl...

Page 222: ...r of 0s to the right of INTVEC_PRC0 in INTC_IACKR_PRC0 The VTES_PRC1 bit controls the number of 0s to the right of INTVEC_PRC1 in INTC_IACKR_PRC1 If the contents of INTC_IACKR_PRC0 or INTC_IACKR_PRC1...

Page 223: ...11 1010 Priority 10 1001 Priority 9 1000 Priority 8 0111 Priority 7 0110 Priority 6 0101 Priority 5 0100 Priority 4 0011 Priority 3 0010 Priority 2 0001 Priority 1 0000 Priority 0 lowest priority Offs...

Page 224: ...set 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R VTBA_PRC0 least significant five bits INTVEC_PRC01 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 When the VTES_PRC...

Page 225: ...te 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R VTBA_PRC1 most significant 16 bits W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R VTBA_PRC1 5 least significant bi...

Page 226: ...0 0 0 0 0 0 Figure 9 8 INTC End of Interrupt Register for Processor 1 Z0 INTC_EOIR_PRC1 Offset 0x0020 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 CLR0 0 0 0 0 0 0 0 CL...

Page 227: ...R292_293 Table 9 8 INTC_SSCIR 0 7 Field Descriptions Field Description SETn Set Flag Bits Writing a 1 sets the corresponding CLRn bit Writing a 0 has no effect Each SETn always will be read as a 0 CLR...

Page 228: ...PSR4_7 0x0044 INTC_PSR152_155 0x00D8 INTC_PSR8_11 0x0048 INTC_PSR156_159 0x00DC INTC_PSR12_15 0x004C INTC_PSR160_163 0x00E0 INTC_PSR16_19 0x0050 INTC_PSR164_167 0x00E4 INTC_PSR20_23 0x0054 INTC_PSR168...

Page 229: ...orresponding peripheral or software settable interrupt request is asserted NOTE When sending an interrupt to both cores the user must take care to prevent the interrupt from going away from the other...

Page 230: ..._n Furthermore clearing the peripheral interrupt request s enable bit in the peripheral or alternatively setting its mask bit has the same consequences as clearing its flag bit Setting its enable bit...

Page 231: ...gher than the current priority for a given processor then the interrupt request to the processor is asserted A unique vector for the preempting peripheral or software settable interrupt request is gen...

Page 232: ...ot need to be loaded from the associated INTC_CPR_PRC0 or INTC_CPR_PRC1 and stored onto the context stack Likewise at the end of the interrupt exception handler the priority does not need to be loaded...

Page 233: ...ception Handler Before the interrupt exception handling completes INTC_SSCIR0_3 INTC_SSCIR4_7 must be written When written the associated LIFO is popped so the preempted priority is restored into PRI...

Page 234: ...dated with the preempting peripheral or software settable interrupt request s vector when the interrupt request to the processor is asserted The INTVEC field retains that value until the next time the...

Page 235: ...ipheral and software settable interrupt requests to cause an interrupt request to the processor is interrupt_request_initialization configure VTES_PRC0 VTES_PRC1 HVEN_PRC0 and HVEN_PRC1 in INTC_MCR co...

Page 236: ...store context required by EABI and disable processor recognition of interrupts code to restore SRR0 and SRR1 rfi vector_table_base_address address of ISR for interrupt with vector 0 address of ISR for...

Page 237: ...If a task shares a resource with an ISR and the PCP is being used to manage that shared resource then the task s priority can be elevated in the INTC_CPR_PRCn while the shared resource is being access...

Page 238: ...ription Code Executing at End of Step PRI in INTC_CPR at End of Step RTOS ISR1081 1 ISR108 executes for peripheral interrupt request 100 because the first eight ISRs are for software settable interrup...

Page 239: ...s responding to the interrupt request from the INTC and as it is aborting transactions and flushing its pipeline it is possible that both stores will be executed ISR2 thereby thinks that it can access...

Page 240: ...an what the later portion of the ISR needs This preemptive scheduling inefficiency reduces the processor s ability to meet its deadlines One option is for the ISR to complete the earlier higher priori...

Page 241: ...ve flag bits that can be cleared as a side effect of servicing a peripheral interrupt request For example reading a specific register can clear the flag bits and their corresponding interrupt requests...

Page 242: ...eeply the LIFO is nested However if he wants to read the contents such as in debug mode they are not memory mapped The contents can be read by popping the LIFO and reading the PRI field in either INTC...

Page 243: ...Interrupt Controller INTC MPC5510 Microcontroller Family Reference Manual Rev 1 9 28 Freescale Semiconductor Preliminary...

Page 244: ...structions are not supported by e200 in hardware but are trapped and may be emulated by software All arithmetic instructions that execute in the core operate on data in the general purpose registers G...

Page 245: ...in a single cycle with the exception of the divide instructions A count leading zeros unit operates in a single clock cycle The instruction unit contains a PC incrementer and a dedicated branch addre...

Page 246: ...Vectored and autovectored interrupts are supported by the CPU Vectored interrupt support is provided to allow multiple interrupt sources to have unique interrupt handlers invoked with no software ove...

Page 247: ...fts and rotates 32 bit mask unit for data masking and insertion Divider logic for signed and unsigned divide in 6 16 clocks with minimized execution timing 32x32 hardware multiplier array supports sin...

Page 248: ...register to register operations for all computational instructions Source data for these instructions are accessed from the on chip registers or are provided as immediate values embedded in the opcode...

Page 249: ...s Compare DAC1 DAC2 SPR 316 SPR 317 1 These e200 specific registers may not be supported by other Power Architecture processors 2 Optional registers defined by the Power Architecture Book E architectu...

Page 250: ...ervisor Mode Program Model DCRs PSU Registers1 PSU PSCR PSSR PSHR PSLR PSCTR PSUHR PSULR DCR 272 DCR 273 DCR 274 DCR 275 DCR 276 DCR 277 DCR 278 1 These e200 specific registers may not be supported by...

Page 251: ...rchitecture Book E provides the mtspr and mfspr instructions for accessing SPRs Integer exception register XER The XER indicates overflow and carries for integer operations See XER Register XER in Cha...

Page 252: ...bers for the cores used on the MPC5510 Family Processor Identification Register PIR This read only register is provided to distinguish the processor from other processors in the system Storage Control...

Page 253: ...ing and configuring debug events Debug Status Register DBSR This register contains debug event status Instruction Address Compare registers IAC1 IAC4 These registers contain addresses and or masks whi...

Page 254: ...Handling and Control Registers Machine Check Syndrome register MCSR This register provides a syndrome to differentiate between the different kinds of conditions which can generate a Machine Check Deb...

Page 255: ...tion of the TLBs System version register SVR This register is a read only register that identifies the version model and revision level of the SoC which includes an e200 Power Architecture processor N...

Page 256: ...and load store units generate 32 bit effective addresses The MMU translates this effective address to a 32 bit real address which is then used for memory accesses The Power Architecture Book E archit...

Page 257: ...uded as part of the virtual address in the translation process AS 10 4 1 3 Process ID The Power Architecture Book E architecture defines that a process ID PID value is associated with each effective a...

Page 258: ...t the generation of the physical address occurs as shown in Figure 10 6 Table 10 3 Page Size and EPN Field Comparison SIZE Field Page Size 4SIZEKbytes EA to EPN Comparison 0b0001 0b0010 0b0011 0b0100...

Page 259: ...e might be execute only data structures may be mapped as read write no execute and can also be changed by the operating system based on application requests and operating system policies The UX SX UW...

Page 260: ...rough a set of special purpose registers MMUCFG TLB0CFG TLB1CFG etc By convention TLB0 is used for a set associative TLB with fixed page sizes TLB1 is used for a fully associative TLB with variable pa...

Page 261: ...32 higher Where appropriate the Book E defined bit numbers are shown in parentheses The MAS0 register is shown in Figure 10 8 Fields are defined in Table 10 5 Table 10 4 TLB Entry Bit Definitions Fie...

Page 262: ...victim for TLBCAM software managed Software updates this field it is copied to the ESELCAM field on a TLB Error VALID IPROT 0 TID 0 TS TSIZ 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 2...

Page 263: ...E 0 3 0b0111 16MB TSIZE 0 3 0b1000 64MB TSIZE 0 3 0b1001 256MB TSIZE 0 3 0b1010 1 GB TSIZE 0 3 0b1011 4 GB All other values are undefined 24 31 56 63 Reserved2 1 Numbers shown in parentheses are the 6...

Page 264: ...Access to this page are not guarded and can be performed before it is known if they are required by the sequential execution model 1 All loads and stores to this page are performed without speculation...

Page 265: ...ad as zero and writes are ignored 22 25 54 57 U0 U3 User bits 0 3 26 31 58 63 PERMIS Permission bits UX SX UW SW UR SR 0 TLBSELD 01 0 TIDSELD 0 TSIZED 0 VLED WD ID MD GD ED 0 1 2 3 4 5 6 7 8 9 10 11 1...

Page 266: ...s are not implemented will be read as zero and writes are ignored 0 SPID 0 SAS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR 630 Read Write Reset Unaffected...

Page 267: ...ating little endian 3 Misaligned Instruction fetch due to a change of flow to an odd halfword instruction boundary on a Book E non VLE instruction page 4 Precise external termination error and MSR EE...

Page 268: ...ned transfers supports true big and little endian operating modes and operates in a pipelined fashion The instruction memory interface supports read transfers of 16 and 32 bits supports misaligned tra...

Page 269: ...e200z1 Core Z1 MPC5510 Microcontroller Family Reference Manual Rev 1 10 26 Freescale Semiconductor Preliminary...

Page 270: ...metic instructions that execute in the core operate on data in the general purpose registers GPRs Instead of the base Power Architecture Book E instruction set support the e200z0 core implements only...

Page 271: ...ycle The instruction unit contains a PC incrementer and a dedicated branch address adder to minimize delays during change of flow operations Sequential prefetching is performed to ensure a supply of i...

Page 272: ...bit VLE instructions per clock Instruction buffer with two entries each holding a single 32 bit instruction or a pair of 16 bit instructions Dedicated PC incrementer supporting instruction prefetches...

Page 273: ...and Programmer s Model This section describes the registers implemented in the e200z0 core It includes an overview of registers defined by the Power Architecture Book E architecture highlighting diff...

Page 274: ...the Power Architecture Book E specification In this document register bits are sometimes numbered from bit 0 most significant bit to 31 least significant bit rather than the Book E numbering scheme o...

Page 275: ...C3 IAC4 SPR 312 SPR 313 SPR 314 SPR 315 Data Address Compare DAC1 DAC2 SPR 316 SPR 317 1 These e200 specific registers may not be supported by other Power Architecture processors 2 Optional registers...

Page 276: ...sters are described in Section 11 3 2 e200 Specific Special Purpose Registers 11 3 1 1 User Level Registers The user level registers can be accessed by all software with either user or supervisor priv...

Page 277: ...ating system functions The Power Architecture Book E defines the following supervisor level registers Processor Control Registers Machine State Register MSR The MSR defines the state of the processor...

Page 278: ...t handler routine Save Restore register 1 SRR1 The SRR1 register is used to save machine state from the MSR on non critical interrupts and to restore machine state when se_rfi executes Critical Save R...

Page 279: ...DSRR0 register is used to save the address of the instruction at which execution continues when se_rfdi executes at the end of a debug interrupt handler routine Debug Save Restore register 1 DSRR1 Wh...

Page 280: ...s registers are not accessible by code running in User or Supervisor mode Nexus registers can be accessed only by external tools via the Nexus port Debug Table 11 3 Exceptions and Conditions Interrupt...

Page 281: ...bits supports misaligned transfers and operates in a pipelined fashion Single beat and misaligned transfers are supported for read and write cycles Incrementing burst transfers are supported for inst...

Page 282: ...mmable channels with minimal intervention from the host processor The hardware microarchitecture includes a DMA engine that performs source and destination address calculations and the actual data mov...

Page 283: ...yte transfer count An outer data transfer loop defined by a major iteration count Channel activation via one of three methods Explicit software initiation Initiation via a channel to channel linking m...

Page 284: ...de the eDMA will not accept new transfer requests when its debug input signal is asserted If the signal is asserted during transfer of a block of data described by a minor loop in the current active c...

Page 285: ..._CER eDMA clear error register W 0x00 12 3 2 10 12 15 8 0x001E EDMA_SSBR eDMA set start bit register W 0x00 12 3 2 11 12 15 8 0x001F EDMA_CDSBR eDMA clear done status bit register W 0x00 12 3 2 12 12...

Page 286: ...x10C0 TCD06 eDMA transfer control descriptor 06 R W 1 12 3 2 16 12 19 256 0x10E0 TCD07 eDMA transfer control descriptor 07 R W 1 12 3 2 16 12 19 256 0x1100 TCD08 eDMA transfer control descriptor 08 R...

Page 287: ...4028 Reserved 0xFFF4_402C Reserved eDMA Error Low EDMA_ERL Channels 15 00 0xFFF4_4030 0xFFF4_40FC Reserved 0xFFF4_4100 eDMA Channel 0 Priority EDMA_CPR0 eDMA Channel 1 Priority EDMA_CPR1 eDMA Channel...

Page 288: ...In round robin arbitration mode the channel priorities are ignored and the channels are cycled through from channel 15 down to channel 0 without regard to priority Offset EDMA_BASE 0x0000 Access User...

Page 289: ...t scatter gather and minor loop link error are reported as the channel is activated and assert an error interrupt request if enabled When properly enabled a scatter gather configuration error is repor...

Page 290: ...mber Channel number of the last recorded error excluding CPE errors Note Do not rely on the number in the ERRCHN field for channel priority errors Channel priority errors must be resolved by inspectio...

Page 291: ...ast recorded error was a configuration error detected in the TCD NBYTES or TCD CITER fields indicating the following conditions exist TCD NBYTES is not a multiple of TCD SSIZE and TCD DSIZE or TCD CIT...

Page 292: ...modify write sequence to the EDMA_EEIRL Both the eDMA error indicator and this error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted 12 3 2 5...

Page 293: ...ERQ 0 provides a global clear function forcing the entire contents of the EDMA_ERQRL to be zeroed disabling all eDMA request inputs Reads of this register return all zeroes Offset EDMA_BASE 0x0018 Acc...

Page 294: ...en channel The data value on a register write causes the corresponding bit in the EDMA_EEIRL to be cleared Setting bit 1 CEEI 0 provides a global clear function forcing the entire contents of the EDMA...

Page 295: ...MA_BASE 0x001B Access User write only 0 1 2 3 4 5 6 7 R 0 0 0 0 0 0 0 0 W CEEI 0 6 Reset 0 0 0 0 0 0 0 0 Figure 12 9 eDMA Clear Enable Error Interrupt Register EDMA_CEEIR Table 12 10 EDMA_CEEIR Field...

Page 296: ...memory mapped mechanism to set the START bit in the TCD of the given channel The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set Setting...

Page 297: ...y setting the appropriate bit in this register The outputs of this register are directly routed to the interrupt controller INTC During the execution of the interrupt service routine associated with a...

Page 298: ...e error interrupt request Typically a write to the EDMA_CER in the interrupt service routine is used for this purpose The normal eDMA channel completion indicators setting the transfer control descrip...

Page 299: ...reempted channel is restored and resumes execution After the restored channel completes one read write sequence it is again eligible for preemption If any higher priority channel requests service the...

Page 300: ...be temporarily suspended by the service request of a higher priority channel bits 1 3 Reserved CHPRI Channel n Arbitration Priority Channel priority when fixed priority arbitration is enabled The res...

Page 301: ...gure 12 17 TCD Structure Table 12 19 TCDn Field Descriptions Bits Word Offset n n Name Description 0 31 0x0 0 31 SADDR 0 31 Source address Memory address pointing to the source data Word 0x0 bits 0 31...

Page 302: ...jor iteration count is decremented and restored to the local memory If the major iteration count is completed additional processing is performed Note The NBYTES value of 0x0000_0000 is interpreted as...

Page 303: ...ted 192 223 0x18 0 31 DLAST_SGA 0 31 Last destination address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel scatter gather If scatter gather...

Page 304: ...nt of bus bandwidth consumed by the eDMA In general as the eDMA processes the inner minor loop it continuously generates read write sequences until the minor count is exhausted This field forces the e...

Page 305: ...cution 252 0x1C 28 D_REQ Disable hardware request If this flag is set the eDMA hardware automatically clears the corresponding EDMA_ERQL bit when the current major iteration count reaches zero 0 The c...

Page 306: ...unt is exhausted additional processing is performed including the final address pointer updates reloading the TCDn CITER field and a possible fetch of the next TCDn from memory as part of a scatter ga...

Page 307: ...4 1 eDMA Basic Data Flow The eDMA transfers data based on a two deep nested flow The basic flow of a data transfer can be partitioned into three segments As shown in Figure 12 18 the first segment inv...

Page 308: ...ched data is temporarily stored in the data path module until it is gated onto the system bus during the destination write This source read destination write processing continues until the inner minor...

Page 309: ...de the final address adjustments and reloading of the BITER field into the CITER Additionally assertion of an optional interrupt request occurs at this time as does a possible fetch of a new TCD from...

Page 310: ...32 byte TCD for each channel that may request service 5 Enable any hardware service requests via the EDMA_ERQRH and or EDMA_ERQRL registers 6 Request channel service by software setting the TCD START...

Page 311: ...nd scatter gather operations if enabled Figure 12 21 shows how each DMA request initiates one minor loop transfer iteration without CPU intervention DMA arbitration can occur after each minor loop and...

Page 312: ...ecorded in the EDMA_ESR If the error source is not removed before the next activation of the problem channel the error will be detected and recorded again DMA request Minor loop 3 Current major loop i...

Page 313: ...vels Table 12 21 DMA Request Summary for eDMA DMA Request Channel Source Description DMA_MUX_CHCONFIG0_SOURCE 0 DMA_MUX CHCONFIG0 SOURCE DMA MUX channel 0 source DMA_MUX_CHCONFIG1_SOURCE 1 DMA_MUX CHC...

Page 314: ...and four bytes for the destination The final source and destination addresses are adjusted to return to their beginning values TCD CITER TCD BITER 1 TCD NBYTES 16 TCD SADDR 0x1000 TCD SOFF 1 TCD SSIZE...

Page 315: ...uests are enabled in the EDMA_ERQR channel service requests are initiated by the slave device ERQR should be set after TCD Note that TCD START 0 TCD CITER TCD BITER 2 TCD NBYTES 16 TCD SADDR 0x1000 TC...

Page 316: ...0x1018 read_byte 0x1019 read_byte 0x101a read_byte 0x101b f write_word 0x2018 third iteration of the minor loop g read_byte 0x101c read_byte 0x101d read_byte 0x101e read_byte 0x101f h write_word 0x201...

Page 317: ...D ACTIVE 1 TCD DONE 0 channel is executing 3 TCD START 0 TCD ACTIVE 0 TCD DONE 0 channel has completed the minor loop and is idle or 4 TCD START 0 TCD ACTIVE 0 TCD DONE 1 channel has completed the maj...

Page 318: ...ated as equal or more exactly constantly rotating when round robin arbitration mode is selected The TCD ACTIVE bit for the preempted channel remains asserted throughout the preemption The preempted ch...

Page 319: ...ing model during channel execution 12 5 8 1 Dynamic Channel Linking and Dynamic Scatter Gather Operation Dynamic channel linking and dynamic scatter gather operation is the process of changing the TCD...

Page 320: ...t was successful b If the bit is cleared the attempted dynamic link did not succeed the channel was already retiring This same coherency model is true for dynamic scatter gather operations For both dy...

Page 321: ...Enhanced Direct Memory Access eDMA MPC5510 Microcontroller Family Reference Manual Rev 1 12 40 Freescale Semiconductor Preliminary...

Page 322: ...ght sources are always enabled and will generate a DMA request as soon as that source is selected One source the default for all channels is always disabled 13 1 1 Block Diagram A simplified block dia...

Page 323: ...he period of a DMA trigger for example Normal mode In this mode a DMA source such as SCI transmit or SCI receive for example is routed directly to the specified DMA channel The operation of the DMA_MU...

Page 324: ...Channel 2 configuration R W 0x00 13 3 2 1 13 3 0x0003 CHCONFIG3 Channel 3 configuration R W 0x00 13 3 2 1 13 3 0x0004 CHCONFIG4 Channel 4 configuration R W 0x00 13 3 2 1 13 3 0x0005 CHCONFIG5 Channel...

Page 325: ...Mode 0 X DMA channel is disabled Disabled mode 1 0 DMA channel is enabled with no triggering transparent Normal mode 1 1 DMA channel is enabled with triggering Periodic trigger mode Table 13 4 DMA Sou...

Page 326: ...STAT1 RXRDY SCI_F combined DMA request of the receive data register full and LIN receive data ready DMA requests SCI_G_COMBTX 0x0D SCI_G SCISR1 TDRE SCI_G SCISR1 TC SCI_G LINSTAT1 TXRDY SCI_G combined...

Page 327: ...nnel 11 flag eMIOS200_FLAG_F12 0x25 eMIOS200 eMIOS200FLAG F12 eMIOS200 channel 12 flag eMIOS200_FLAG_F13 0x26 eMIOS200 eMIOS200FLAG F13 eMIOS200 channel 13 flag eMIOS200_FLAG_F14 0x27 eMIOS200 eMIOS20...

Page 328: ...frames or packets at fixed intervals without the need for processor intervention The trigger is generated by the periodic interrupt timer PIT as such the configuration of the periodic triggering inte...

Page 329: ...e DMA until a trigger event has been seen This is illustrated in Figure 13 4 Figure 13 4 DMA_MUX Channel Triggering Normal Operation After the DMA request has been serviced the peripheral negates its...

Page 330: ...s as an example On the receive side of the SPI the SPI and DMA can be configured to transfer receive data into memory effectively implementing a method to periodically read data from external devices...

Page 331: ...ast as possible or periodically using the DMA triggering capability Doing DMA transfers from memory to memory Moving data from memory to memory typically as fast as possible sometimes with software ac...

Page 332: ...always enabled source Note that the re activation of the channel can be continuous DMA triggering is disabled or can use the DMA triggering capability In this manner it is possible to execute periodic...

Page 333: ...unsigned char CHCONFIG12 volatile unsigned char DMAMUX_BASE_ADDR 0x000C volatile unsigned char CHCONFIG13 volatile unsigned char DMAMUX_BASE_ADDR 0x000D volatile unsigned char CHCONFIG14 volatile uns...

Page 334: ...IG2 0x00 CHCONFIG2 0x85 13 5 2 3 Disabling a Source A particular DMA source may be disabled by not writing the corresponding source value into any of the CHCONFIG registers Some module specific config...

Page 335: ...ADDR 0x0008 volatile unsigned char CHCONFIG9 volatile unsigned char DMAMUX_BASE_ADDR 0x0009 volatile unsigned char CHCONFIG10 volatile unsigned char DMAMUX_BASE_ADDR 0x000A volatile unsigned char CHCO...

Page 336: ...HB 2 v6 AMBA AHB lite version 2 0 with v6 extensions AMBA AHB Lite Interface A standard AHB lite bus interface AIPS AHB 2 v6 to IPS interface unit IPS IP slave interface A Freescale Intellectual Prope...

Page 337: ...bit boundary are not supported The peripherals connected to the AIPS lite may be configured in groups to run at less than the system clock frequency See Section 3 4 5 Peripheral Clock Dividers in Chap...

Page 338: ...a description of which peripherals are allocated to which 16 KB memory space in the AIPS lite address map 14 4 1 Read Cycles Two clock read accesses are possible with the AIPS Lite when the reference...

Page 339: ...Peripheral Bridge AIPS lite MPC5510 Microcontroller Family Reference Manual Rev 1 14 4 Freescale Semiconductor Preliminary...

Page 340: ...re than one master port arbitration logic will select the appropriate master and grant it ownership of the slave port By default requesting masters will be treated with round robin priority and will b...

Page 341: ...purposes only Z0 core master ID 1 XBAR m5 Z1 core Data master ID 0 XBAR m4 Z1 core Instruction master ID 0 XBAR m0 Nexus 2 pretending to be Z0 core master ID 9 Nexus 2 pretending to be Z1 core master...

Page 342: ...n by the XBAR If the targeted slave port of the access is available i e the requesting master is currently granted ownership of the slave port the access will be immediately presented on the slave por...

Page 343: ...ority master gains control of the slave port once the other master releases control of the slave port as long as no other higher priority master is also waiting for the slave port A master access is t...

Page 344: ...ast master of the slave port was master 1 and masters 0 4 and 5 make simultaneous requests they will be serviced in the order 4 5 and then 0 Parking may still be used in a round robin mode but will no...

Page 345: ...cle or runs a non IDLE cycle to a location other than the current slave port 15 4 4 Slave Port State Machine 15 4 4 1 Slave Port State Machine Arbitration The real work in the state machine is determi...

Page 346: ...configured for parking on the last master ownership remains with the last master to access the slave port until another master requests an access Figure 15 3 illustrates parking on the last master On...

Page 347: ...associated with the XBAR 1 Hardwired and not user changeable configuration for slave port s3 1 2 3 4 5 6 7 8 9 Master 0 None Master 2 None Master 4 None None Arbitration Master 0 Arbitration Master 2...

Page 348: ...cation is set that the error occurred A non correctable ECC error is generated when two or more bits in a 64 bit doubleword are incorrect Non correctable ECC errors cause an interrupt and if enabled a...

Page 349: ...er is given as an offset to the MCM base address Registers are listed in address order identified by complete name and mnemonic and lists the type of accesses allowed Table 16 1 MCM Memory Map Offset...

Page 350: ...T Interrupt SWTIR 0x0020 0x0023 Reserved 0x0024 Miscellaneous User Defined Control Register MUDCR 0x0028 0x003C Reserved 0x0040 Reserved ECC Configuration ECR 0x0044 Reserved ECC Status ESR 0x000048 R...

Page 351: ...atchdog timer interrupt or a hardware reset as programmed in the SWTCR SWRI There are three user defined responses to a time out The SWTCR SWRI can specify the assertion of a watchdog timer interrupt...

Page 352: ...rols the software watchdog timer time out periods and time out response The register can be read or written at any time At system reset the software watchdog timer is enabled See Figure 16 1 and Table...

Page 353: ...he highest priority interrupt level is used to signal the SWT 01 The first time out sets the SWTIC watchdog interrupt flag and the SWT generates an interrupt request to the system If the SWTIC watchdo...

Page 354: ...rrupt response to a time out For these configurations the SWTIR provides the program visible interrupt request from the software watchdog timer 16 2 2 4 Miscellaneous User Defined Control Register MUD...

Page 355: ...o a change of flow operation and buffered operand writes The ECC reporting logic in the MCM provides an optional error interrupt mechanism to signal all non correctable memory errors In addition to th...

Page 356: ...he address and attribute reporting registers 3 Re read the ESR and verify the current contents matches the original contents If the two values are different repeat from step one 4 When the values are...

Page 357: ...nition Offset MCM_BASE_ADDR 0x0047 Access User read write 0 1 2 3 4 5 6 7 R 0 0 0 0 0 0 RNCE FNCE W w1c w1c Reset 0 0 0 0 0 0 0 0 Figure 16 6 ECC Status ESR Register Table 16 7 ESR Field Descriptions...

Page 358: ...position specified in ERRBIT and the overall odd parity bit on the first write operation after this bit is set The normal ECC generation takes place in the RAM controller but then the polarity of the...

Page 359: ...ster number of the last properly enabled ECC event in the flash memory Depending on the state of the ECC Configuration Register an ECC event in the flash causes the address attributes and data associa...

Page 360: ...ly any attempted write is ignored See Figure 16 10 and Table 16 11 for the flash ECC attributes register definition Table 16 10 FEMR Field Descriptions Field Description bits 0 3 Reserved FEMR Flash C...

Page 361: ...e 16 12 for the flash ECC data register definition 16 2 2 5 8 RAM ECC Address Register REAR The REAR is a 32 bit register for capturing the address of the last properly enabled ECC event in the RAM me...

Page 362: ...ributes Register REAT The REAT is an 8 bit register for capturing the AXBS bus master attributes of the last properly enabled ECC event in the RAM memory Depending on the state of the ECC configuratio...

Page 363: ...vent in the RAM causes the address attributes and data associated with the access to be loaded into the REAR RESR REMR REAT and REDR registers and also the appropriate flag RNCE in the ECC status regi...

Page 364: ...ould be enabled If the corresponding processor is configured to allow high priority elevation on critical interrupt events the MCM generates the high priority signal upon critical interrupt detection...

Page 365: ...Miscellaneous Control Module MCM MPC5510 Microcontroller Family Reference Manual Rev 1 16 18 Freescale Semiconductor Preliminary...

Page 366: ...sufficient access control rights are allowed to complete but references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response The MP...

Page 367: ...maining three non core bus masters DMA FlexRay and EBI support read write attributes Automatic hardware maintenance of the region descriptor valid bit removes issues associated with maintaining a cohe...

Page 368: ...upport any special modes of operation 17 2 Signal Description The MPU does not include any external signals 17 3 Memory Map and Registers This section provides a detailed description of all MPU regist...

Page 369: ...tor 10 R W 1 17 3 2 4 17 7 0x04B0 MPU_RGD11 MPU region descriptor 11 R W 1 17 3 2 4 17 7 0x04C0 MPU_RGD12 MPU region descriptor 12 R W 1 17 3 2 4 17 7 0x04D0 MPU_RGD13 MPU region descriptor 13 R W 1 1...

Page 370: ...2 MPU RGD alternate access control 12 W 1 17 3 2 5 17 12 0x0834 MPU_RGDAAC13 MPU RGD alternate access control 13 W 1 17 3 2 5 17 12 0x0838 MPU_RGDAAC14 MPU RGD alternate access control 14 W 1 17 3 2 5...

Page 371: ...PU_EDRn registers do contain an unread captured error Note Bit 0 indicates a flash port 0 access protection error bit 1 a combined Flash Port 1 EBI peripheral bridge protection error and bit 3 an SRAM...

Page 372: ...Ded with the access error indication The MPU performs a reference by reference evaluation to determine the presence absence of an access error When an error is detected the hit qualified access contro...

Page 373: ...s well as the optional inclusion of a process identification field within the definition Bus masters 4 7 are typically reserved for data movement engines and their capabilities are limited to separate...

Page 374: ...nored for these masters Writes to this word clear the region descriptor s valid bit Because it is also expected that system software may adjust only the access controls within a region descriptor MPU_...

Page 375: ...and execute allowed but no write 10 r w read and write allowed but no execute 11 Same access controls as that defined by M2UM for user mode M2UM Bus Master ID 2 User Mode Access Control This 3 bit fie...

Page 376: ...provided If only the access controls are being updated this operation must be performed by writing to MPU_RGDAACn alternate access control n as stores to these locations do not affect the descriptor...

Page 377: ...field is combined with the PIDMASK and included in the region hit determination if MPU_RGDn Word2 MxPE is set PIDMASK Process Identifier Mask This 8 bit field provides a masking capability so that mu...

Page 378: ...00 r w x read write and execute allowed 01 r x read and execute allowed but no write 10 r w read and write allowed but no execute 11 Same access controls as that defined by M2UM for user mode M2UM Bus...

Page 379: ...s not a schematic of the actual access evaluation macro but a generalized block diagram showing the major functions included in this logic block M0SM Bus Master 0 Supervisor Mode Access Control This 2...

Page 380: ...ask 0 7 rgdn pid 0 7 rgdn pidmask 0 7 where the current_pid is the selected process identifier from the current bus master and rgdn pid and rgdn pidmask are the appropriate process identifier fields f...

Page 381: ...hits in a single region descriptor and that region signals a protection violation a protection error is reported 3 If the access hits in multiple overlapping regions and all regions signal protection...

Page 382: ...on switch instantaneously to the new value as the IPS write completes 3 If the region s start and end addresses are to be changed this would typically be performed by writing a minimum of three words...

Page 383: ...e logical OR of the two region descriptors Thus CP0 has rw r rw permissions while CP1 has r r permission in this space Both DMA engines are excluded from this shared processor data region The overlapp...

Page 384: ...needed in multi core systems for implementing semaphores and provide a simple mechanism to achieve lock unlock operations via a single write access This approach eliminates architecture specific impl...

Page 385: ...atures Support for 16 hardware enforced gates in a dual processor configuration Each hardware gate appears as a three state 2 bit state machine with all 16 gates mapped as an array of bytes Three stat...

Page 386: ...the state of the semaphore gate 18 1 3 Modes of Operation The semaphores module does not support any special modes of operation 18 2 Signal Description The semaphores module does not include any exter...

Page 387: ...00A SEMA4_Gate10 Semaphores gate 10 R W 0x00 18 3 2 1 18 4 0x000B SEMA4_Gate11 Semaphores gate 11 R W 0x00 18 3 2 1 18 4 0x000C SEMA4_Gate12 Semaphores gate 12 R W 0x00 18 3 2 1 18 4 0x000D SEMA4_Gate...

Page 388: ...rrupt to return its execution to the original lock function The optional notification interrupt function consists of two registers for each processor an interrupt notification enable register SEMA4_CP...

Page 389: ...mplementation specifies a protocol where the locking processor must unlock the gate it is recognized that system operation may require a reset function to re initialize the state of any gate s without...

Page 390: ...pper byte SEMA4_RSTGT RSTGDP is the logical complement of the first data pattern 0x1d and the lower byte SEMA4_RSTGT RSTGTN specifies the gate s to be reset This gate field can specify a single gate b...

Page 391: ...machine is maintained in a 2 bit three state implementation defined as 00 Idle waiting for the first data pattern write 01 Waiting for the second data pattern write 10 The 2 write sequence has complet...

Page 392: ...0 RSTNMS RSTNTN W RSTNDP Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 18 6 SEMA4_RSTGT Field Descriptions Field Description RSTNSM Reset Notification Finite State Machine The reset state machine is ma...

Page 393: ...protected by a gate variable After a processor locks a gate accesses to the shared data or resources by other processes processors must be blocked This is enforced by software conventions The processo...

Page 394: ...ber of semaphores versus the infinite number that can be supported with PowerPC reservation instructions 18 4 1 Semaphore Usage Example 1 Inter processor communication done with software interrupts an...

Page 395: ...lves reads and writes to the SEMA4_GATEn registers for implementation of the hardware enforced software gate functions Typical code segments for gate functions perform the following operations To lock...

Page 396: ...used to move the contents of the PIR into a general purpose register mfspr rx 286 where rx is the destination GPRn Other architectures may support a specific instruction to move the contents of the l...

Page 397: ...Semaphores MPC5510 Microcontroller Family Reference Manual Rev 1 18 14 Freescale Semiconductor Preliminary...

Page 398: ...t to and output from the JTAGC is communicated in serial format 19 1 1 Block Diagram A simplified block diagram of the JTAGC illustrates the functionality and interdependence of major blocks see Figur...

Page 399: ...ivate MCU specific instructions Three test data registers a bypass register a boundary scan register and a device identification register The size of the boundary scan register is 276 bits A TAP contr...

Page 400: ...truction is current Only one test data register path is enabled to shift data between TDI and TDO for each instruction The boundary scan register is enabled for serial access between TDI and TDO when...

Page 401: ...r allows instructions to be loaded into the module to select the test to be performed or the test data register to be accessed or both Instructions are shifted in through TDI while the TAP controller...

Page 402: ...y Scan The size of the boundary scan register is 276 bits 19 4 Functional Description 19 4 1 JTAGC Reset Configuration While in reset the TAP controller is forced into the test logic reset state thus...

Page 403: ...en TDI and TDO though the selected register starting with the least significant bit as illustrated in Figure 19 5 This applies for the instruction register test data registers and the bypass register...

Page 404: ...te State Machine TEST LOGIC RESET RUN TEST IDLE SELECT DR SCAN SELECT IR SCAN CAPTURE DR CAPTURE IR SHIFT DR SHIFT IR EXIT1 DR EXIT1 IR PAUSE DR PAUSE IR EXIT2 DR EXIT2 IR UPDATE DR UPDATE IR 1 0 1 1...

Page 405: ...uctions The JTAGC implements the IEEE 1149 1 2001 defined instructions listed in Table 19 2 This section gives an overview of each instruction refer to the IEEE 1149 1 2001 standard for more details T...

Page 406: ...00z0 OnCE controller register descriptions 19 4 4 3 CLAMP Instruction CLAMP allows the state of signals driven from MCU pins to be determined from the boundary scan register while the bypass register...

Page 407: ...e instruction obtains a sample of the system data and control signals present at the MCU input pins and immediately before the boundary scan register cells at the output pins This sampling occurs on t...

Page 408: ...er as the e200z0 OnCE controller and is fully documented in the e200z1 Reference Manual NOTE The register select field in the e200z1 OnCE command register OCMD RS does not implement the shared nexus c...

Page 409: ...fect each core The SNC register requires a new encoding in the OnCE command register s register select field OCMD RS as defined in Section 19 5 3 1 OnCE Command Register OCMD 19 5 3 1 OnCE Command Reg...

Page 410: ...Reserved 010 0000 Instruction Address Compare 1 IAC1 010 0001 Instruction Address Compare 2 IAC2 010 0010 Instruction Address Compare 3 IAC3 010 0011 Instruction Address Compare 4 IAC4 010 0100 Data...

Page 411: ...0 0 0 0 Figure 19 9 OnCE Shared Nexus Control Register SNC Table 19 4 SNC Bit Description Field Description bits 0 21 Reserved DBGRE EVTI Debug Request Enable 00 Disabled x1 EVTI is used for debug re...

Page 412: ...are selected to provide the development support interface for MPC5510 The NDI block interfaces to the e200z1 e200z0 and internal buses to provide development support as per the IEEE ISTO 5001 2003 st...

Page 413: ...nality and interdependence of major blocks see Figure 20 2 and how the individual Nexus blocks are combined to form the NDI Figure 20 1 NDI Functional Block Diagram Power on TCK JCOMP EVTO MSEO MDO re...

Page 414: ...c allowing the development tool to interpolate what transpires between the discontinuities Thus static code may be traced TDO Cross bar Power on JCOMP MCKO EVTO MDO 7 0 MSEO PPC reset BP WP control On...

Page 415: ...oad capabilities All features are independently configurable and controllable via the IEEE 1149 1 I O port The NDI block reset is controlled with JCOMP power on reset and the TAP state machine All the...

Page 416: ...t messages All trace features are enabled or can be enabled by writing the configuration registers via the JTAG port Four MDO pins are available Unused MDO pins can be used as GPIO Details on GPIO fun...

Page 417: ...and a register index OnCE registers are accessed by loading the appropriate value in the RS field of the OnCE command register OCMD via the JTAG port 20 4 1 Nexus Debug Interface Registers Table 20 2...

Page 418: ...0b0000 10 Read write access data RWD 0b0000 11 e200z0 watchpoint trigger PPC_WT 1 Implemented in NPC block All other registers implemented in e200z0 Nexus2 block This register is not used on the MPC55...

Page 419: ...division must not be modified after MCKO has been enabled Changing the mode or clock division while MCKO is enabled can produce unpredictable results PIN Part Identification Number Contains the part...

Page 420: ...being transmitted 0 MCKO gating is disabled 1 MCKO gating is enabled MCKO_EN MCKO Enable This bit enables the MCKO clock to run When enabled the frequency of MCKO is determined by the MCKO_DIV field 0...

Page 421: ...before a pending entry into stop mode After reading STOP_SYNC as set the debug tool then clears STOP_SYNC to acknowledge to the device that it may enter into stop mode 0 Stop mode entry acknowledge 1...

Page 422: ...for BTM DTM OTM overruns 1XX Reserved EIC EVTI Control 00 EVTI is used for synchronization program trace data trace 01 EVTI is used for debug request 1X Reserved TM Trace Mode Any or all of the TM bi...

Page 423: ...xus1 triggers EVTO X1XXXXXX Watchpoint 1 IAC2 from Nexus1 triggers EVTO XX1XXXXX Watchpoint 2 IAC3 from Nexus1 triggers EVTO XXX1XXXX Watchpoint 3 IAC4 from Nexus1 triggers EVTO XXXX1XXX Watchpoint 4...

Page 424: ...n checkstop state bits 24 0 Reserved Nexus Reg 0x0007 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R AC RW SZ MAP PR BST 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15...

Page 425: ...ses are single bus cycle at a time 1 Module accesses are performed as burst operation bits 20 16 Reserved CNT Access Control Count Number of accesses of word size SZ ERR Read Write Access Error See Ta...

Page 426: ...r read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PTS PTE DTS DTE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 427: ...been loaded the client is enabled by loading its NEXUS ENABLE instruction The NEXUS ENABLE instruction opcode for each Nexus client is listed in Table 20 12 Opcodes for all other instructions support...

Page 428: ...ruction Opcodes to Enable Nexus Clients JTAGC Instruction Opcode Description ACCESS_AUX_TAP_NPC 10000 Enables access to the NPC TAP controller ACCESS_AUX_TAP_ONCE 10001 Enables access to the e200z1 TA...

Page 429: ...ammable MCKO Frequency MCKO is an output clock to the development tools used for the timing of MSEO and MDO pin functions MCKO is derived from the system clock and its frequency is determined by the v...

Page 430: ...drives EVTO for two system clock periods EVTO sharing is active as long as the NDI is not in reset 20 5 7 Nexus2 DMA Control The shared Nexus2 implementation allows each core to perform DMA access ind...

Page 431: ...request the EOC field in the e200z0 Nexus2 development control register 1 DC1 must be set to enable the assertion of the event out signal on the occurrence of a watchpoint entry into debug mode or up...

Page 432: ...to follow the z1 into debug mode Assert System Reset Enable Nexus Select NPC PCR Register and Configure FPM MCK_EN EVT_EN and MCK fields Access Nexus Dev Control Register 1 Configure EOC Field EVTO C...

Page 433: ...bit reset signal functions much like the IEEE 1149 1 2001 defined TRST signal but has a default value of disabled JCOMP is pulled low during reset The IEEE 1149 1 2001 defines TRST to be pulled up ena...

Page 434: ...The MPC5510 provides 80 KB of general purpose system SRAM that is implemented using ten 8 KB arrays This implementation allows a configurable number of arrays to remain powered during low power sleep...

Page 435: ...r of 8 KB blocks powered during low power sleep Byte halfword and word addressable Error correcting code ECC performs single bit correction double bit detection on a 32 bit boundary SRAM A 8 KB CRP_PS...

Page 436: ...ory Map and Registers This section provides an array memory map of the SRAM There are no registers associated with the SRAM 21 3 1 Array Memory Map Table 21 1 list the addresses ranges of the SRAM who...

Page 437: ...n with the bus cycle as well as setting the PRNCE bit in the MCM s ESR During a write operation for 8 bit and 16 bit writes a read of 32 bit data will be checked for ECC prior to merging in the write...

Page 438: ...f enabled The user code must re initialize the RAM after any of the above resets otherwise an ECC event might occur 21 5 DMA Requests There are no DMA requests associated with the system SRAM 21 6 Int...

Page 439: ...ted from the read modify write operation which occurs when a write transfer of less than 32 bits or unaligned write is requested Without writing an address to a known value first a read from this addr...

Page 440: ...s arranged as two functional units The first functional unit is the flash core FC The FC is composed of arrayed non volatile storage elements sense amplifiers row selects column selects charge pumps a...

Page 441: ...ripheral bus Figure 22 2 Flash System Block Diagram Low address space High address space Mid address space Flash array blocks Low address space 256 KB Mid address space 256 KB High address space 1 MB...

Page 442: ...er mode stop mode and disable mode These modes are briefly described in this section User mode is the default operating mode of the flash module In this mode it is possible to read and write program a...

Page 443: ...the flash array controller to determine operating configurations These are part of the flash array controller s configuration registers mapped into the IPS address space but are described herein These...

Page 444: ...Table 22 2 Flash Configuration Register Memory Map Offset from FLASH_REGS_BASE 0xFFFF_8000 Register Access Reset Value Section Page 0x0000 MCR Module configuration register R W1 1 Some bits are read...

Page 445: ...8 KB blocks in mid address space EER ECC Event Error EER provides information on previous reads If a double bit detection occurred the EER bit will be set to 1 This bit must then be cleared or a reset...

Page 446: ...indicates the completion status of the PGM sequence This happens in an erase suspended program operation 0 Program or erase operation failed 1 Program or erase operation successful 23 Reserved 24 PRD...

Page 447: ...ase suspend and clear DONE while EHV is low ESUS is cleared on reset 0 Erase sequence is not suspended 1 Erase sequence is suspended 31 EHV Enable High Voltage Enables the flash module for a high volt...

Page 448: ...MCR bits simultaneously only the bit with the highest priority level will be written Setting two bits with the same priority level is prevented by existing write locks and will not put the flash in an...

Page 449: ...r cleared by register writes This bit is a status bit only It may not be written or cleared and the reset value is 0 To set this bit write a password and if the password matches the LME bit will be se...

Page 450: ...h bits 16 21 Reserved LLOCK 9 0 Low Address Block Lock These bits have the same description and attributes as MLOCK As an example of how the LLOCK bits are used if a configuration has sixteen 16 KB bl...

Page 451: ...0 0 0 0 0 0 0 0 0 0 SSLOCK 1 1 SMLOCK 1 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 1 1 1 1 1 1 SLLOCK 9 0 W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figur...

Page 452: ...Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSEL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 LS...

Page 453: ...Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0...

Page 454: ...p0 of the PFLASH2P_H7Fb This register also has two bits ARB and PRI to control arbitration between the p0 p1 ports The PFLASH configuration register for port 1 PFCRP1 is used to specify operation of...

Page 455: ...produces a buffer hit For PFCRP0 this field is set to 0b0000 by hardware reset For PFCRP1 this field is set to 0b0011 by hardware reset xx00 All four buffers are available for any flash access i e th...

Page 456: ...e Wait State Control Used to control the number of wait states to be added to the best case flash array access time for writes This field must be set to a value corresponding to the operating frequenc...

Page 457: ...page buffering to allow sequential reads to be done with higher performance This can create a data coherency issue that must be handled with software Data coherency can be an issue after a program er...

Page 458: ...ntly lock or unlock each block in high mid and low address space against program and erase Two hardware locks are also provided to enable disable the FC for program erase See Section 22 5 4 1 Software...

Page 459: ...address to be programmed Program may be initiated with the 0 to 1 transition of the MCR PGM bit or by clearing the MCR EHV bit at the end of a previous program This first write is referred to as an in...

Page 460: ...suspend PGM 0 User mode read state PEG 0 Read MCR DONE 1 DONE 0 Write MCR PSUS 0 EHV 1 Abort WRITE EHV 0 Step 5 Step 6 PEG Success PEG 1 Write MCR Failure PEG 0 Step 7 EHV 0 PGM more words Step 8 No Y...

Page 461: ...module is not suspended until MCR DONE 1 At this time flash core reads may be attempted After it is suspended the flash core may be read only Reads to the blocks being programmed erased return indete...

Page 462: ...be aborted by clearing MCR EHV assuming MCR DONE is low MCR EHV is high and MCR ESUS is low An erase abort forces the module to step 8 of the erase sequence An aborted erase will result in MCR PEG bei...

Page 463: ...EHV If a program sequence is initiated the value of the MCR PEAS is not reset These values are fixed at the time of the first interlock of the erase Flash core reads from the blocks being erased whil...

Page 464: ...or erase the main address space User mode read state Write MCR ERS 1 Select blocks Erase interlock write Step 1 Step 2 Step 3 Write MCR EHV 1 High voltage active Access MCR DONE Step 4 WRITE ESUS 1 R...

Page 465: ...r restrictions to programming the array in terms of how ECC is calculated See Section 22 5 4 Flash Programming for more information Only one program is allowed per 64 bit ECC segment between erases Er...

Page 466: ...Flash Array and Control MPC5510 Microcontroller Family Reference Manual Rev 1 Freescale Semiconductor 22 27 Preliminary 22 7 Interrupt Requests The flash has no interrupt requests...

Page 467: ...Flash Array and Control MPC5510 Microcontroller Family Reference Manual Rev 1 22 28 Freescale Semiconductor Preliminary...

Page 468: ...OS200 output channels and deserializes the received data by placing it on the eMIOS200 input channels Combined serial interface CSI configuration where the DSPI operates in both SPI and DSI configurat...

Page 469: ...cy updates to SPI queues Programmable SPI transfer attributes on a per frame basis Eight clock and transfer attribute registers Serial clock with programmable polarity and phase Programmable delays PC...

Page 470: ...derrun slave only and SPI mode the slave is asked to transfer data when the TX FIFO is empty FIFO overrun serial frame received while RX FIFO is full Modified transfer formats for communication with s...

Page 471: ...I cannot initiate serial transfers in slave mode 23 1 3 3 Module Disable Mode The module disable mode is used for MCU power management The clock to the non memory mapped logic in the DSPI is stopped w...

Page 472: ...I clock and transfer attributes register 7 R W 0x8400_0000 23 3 2 3 23 9 0x002C DSPI_SR DSPI status register R 0x0200_0000 23 3 2 4 23 17 0x0030 DSPI_RSER DSPI DMA interrupt request select and enable...

Page 473: ...onfigures the DSPI for either master mode or slave mode 0 DSPI is in slave mode 1 DSPI is in master mode CONT_SCKE Continuous SCK Enable Enables the serial communication clock SCK to run continuously...

Page 474: ...inactive state of PCSn is low 1 The inactive state of PCSn is high bit 16 Reserved MDIS Module Disable Allows the clock to be stopped to the non memory mapped logic in the DSPI effectively putting th...

Page 475: ...n The table below lists the various delayed sample points bits 24 30 Reserved HALT Halt Provides a mechanism for software to start and stop DSPI transfers See Section 23 4 2 Start and Stop of DSPI Tra...

Page 476: ...ers is used on a per frame basis When the DSPI is configured as an SPI bus slave the DSPI_CTAR0 register is used When the DSPI is configured as a DSI master the DSICTAS field in the DSPI DSI configura...

Page 477: ...x0018 DSPI_CTAR3 0x001C DSPI_CTAR4 0x0020 DSPI_CTAR5 0x0024 DSPI_CTAR6 0x0028 DSPI_CTAR7 Access Read Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R DBR FMSZ CPOL CPHA LSB FE PCSSCK PASC PDT PBR W Reset...

Page 478: ...elow and Section 23 4 7 1 Baud Rate Generator for details on how to compute the baud rate If the overall baud rate is divide by two or divide by three of the system clock then the continuous SCK enabl...

Page 479: ...n serial devices the devices must have identical clock phase settings 0 Data is captured on the leading edge of SCK and changed on the following edge 1 Data is changed on the leading edge of SCK and c...

Page 480: ...n Table 23 4 details how to compute the delay after transfer PBR Baud Rate Prescaler Selects the prescaler value for the baud rate This field is used in master mode only The baud rate is the frequency...

Page 481: ...able below lists the scaler values The PCS to SCK delay is a multiple of the system clock period and it is computed according to the following equation Note See Section 23 4 7 2 PCS to SCK Delay tCSC...

Page 482: ...table below lists the scaler values The after SCK delay is a multiple of the system clock period and it is computed according to the following equation Note See Section 23 4 7 3 After SCK Delay tASC f...

Page 483: ...beginning of the next frame The table below lists the scaler values The delay after transfer is a multiple of the system clock period and it is computed according to the following equation Note See Se...

Page 484: ...ower saving mechanisms BR Baud Rate Scaler Selects the scaler value for the baud rate This field is used in master mode only The pre scaled system clock is divided by the baud rate scaler to generate...

Page 485: ...of Queue Flag Indicates that transmission in progress is the last entry in a queue The EOQF bit is set when the TX FIFO entry has the EOQ bit set in the command halfword and after the last incoming d...

Page 486: ...er when the RX FIFO is empty 0 RX FIFO is empty 1 RX FIFO is not empty Note In the interrupt service routine RFDF must be cleared only after the DSPI_POPR register is read bit 15 Reserved TXCTR TX FIF...

Page 487: ...abled 1 EOQF interrupt requests are enabled TFUF_RE Transmit FIFO Underflow Request Enable The TFUF_RE bit enables the TFUF flag in the DSPI_SR to generate an interrupt request 0 TFUF interrupt reques...

Page 488: ...a DMA request 0 RFDF interrupt requests or DMA requests are disabled 1 RFDF interrupt requests or DMA requests are enabled RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select Selects between...

Page 489: ...Provides a means for host software to signal to the DSPI that the current SPI transfer is the last in a queue At the end of the transfer the EOQF bit in the DSPI_SR is set 0 The SPI data is not the l...

Page 490: ...3 DSPI_TXFRn The DSPI_TXFRn registers provide visibility into the TX FIFO for debugging purposes Each register is an entry in the TX FIFO The registers are read only and cannot be modified Reading th...

Page 491: ...hat is DSPI_RXFR0 DSPI_RXFR3 are used Offset DSPI_BASE 0x003C DSPI_TXFR0 0x0040 DSPI_TXFR1 0x0044 DSPI_TXFR2 0x0048 DSPI_TXFR3 Access Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TXCMD W Reset 0 0 0 0...

Page 492: ...0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R RXDATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23 10 DSPI Receive FIFO Registers 0 3 DSPI_...

Page 493: ...e DSPI_COMPR is compared with the DSPI_SDR or DSPI_ASDR to detect a change in data Refer to Section 23 4 4 5 DSI Transfer Initiation Control for more information 0 Change in data transfer operation di...

Page 494: ...5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R SER_DATA 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 495: ...is memory mapped so that host software can read the incoming DSI frames Table 23 13 DSPI_ASDR Field Description Field Description bits 0 15 Reserved ASER_DATA 15 0 Alternate Serialized Data The ASER_D...

Page 496: ...he DSPIx_CTAR0 DSPIx_CTAR7 registers hold clock and transfer attributes The manner in which a CTAR is selected depends on the DSPI configuration SPI DSI or CSI The SPI configuration can select which C...

Page 497: ...description of the DSPIx_DSCIR is located in Section 23 3 2 10 DSPI DSI Configuration Register DSPI_DSICR The DSISCTAS field in the DSPIx_DSICR selects which of the DSPIx_CTARs will be used to set th...

Page 498: ...t off yet See Section 23 4 12 Power Saving Features for more details on the halt mode 23 4 1 5 Debug Mode The debug mode is used for system development and debugging If the MCU enters debug mode while...

Page 499: ...Section 23 4 3 5 Receive First In First Out RX FIFO Buffering Mechanism The interrupt and DMA request conditions are described in Section 23 4 11 DMA and Interrupt Conditions Figure 23 17 shows an exa...

Page 500: ...O disable mechanisms allow SPI transfers without using the TX FIFO or RX FIFO The DSPI operates as a double buffered simplified SPI when the FIFOs are disabled The TX and RX FIFOs are disabled separat...

Page 501: ...the state of the TX FIFO is unchanged No error condition is indicated 23 4 3 4 2 Draining the TX FIFO The TX FIFO entries are removed drained by shifting SPI data out through the shift register Entrie...

Page 502: ...remove pop entries from the RX FIFO by reading the DSPIx_POPR For more information on DSPIx_POPR refer to Section 23 3 2 7 DSPI POP RX FIFO Register DSPI_POPR A read of the DSPIx_POPR decrements the R...

Page 503: ...Ix_CTAR1 If the CID bit in the DSPIx_DSICR is set and the data in the DSPIx_COMPR differs from the selected source of the serialized data the slave DSPI will assert the MTRIG signal 23 4 4 3 DSI Seria...

Page 504: ...DDR Figure 23 19 DSI Deserialization Diagram 23 4 4 5 DSI Transfer Initiation Control Data transfers for a master DSPI in DSI configuration are initiated by a condition When chaining DSPIs the master...

Page 505: ...PR a new DSI frame is transmitted The TXSS bit in the DSPIx_DSICR selects which register the DSPIx_COMPR is compared to The MTRIG output signal is asserted every time a change in data is detected 23 4...

Page 506: ...IU IMUX2 See Table 6 23 1 eMIOS output channel 1 1 Set by SIU IMUX2 See Table 6 23 2 eMIOS output channel 2 2 Set by SIU IMUX2 See Table 6 23 3 eMIOS output channel 3 3 Set by SIU IMUX2 See Table 6 23...

Page 507: ...nnel 4 4 Set by SIU IMUX2 See Table 6 23 5 eMIOS output channel 5 5 Set by SIU IMUX2 See Table 6 23 6 eMIOS output channel 6 6 Set by SIU IMUX2 See Table 6 23 7 eMIOS output channel 7 7 Set by SIU IMU...

Page 508: ...rom the TX FIFO The data returned from the bus slave is either used to drive the parallel output signals to the eMIOS or is stored in the RX FIFO CSI configuration Table 23 21 DSPI_D Connectivity Tabl...

Page 509: ...st configure the DSPI so the two CTARs associated with DSI data and SPI data assert different peripheral chip select signals denoted in the figure as PCSx and PCSy The CSI configuration is only suppor...

Page 510: ...s the source of the serialized data and asserts the appropriate CS signal 23 4 5 2 CSI Deserialization The deserialized frames in CSI configuration go into the DSPIx_SDR or the RX FIFO based on the tr...

Page 511: ...PI block guide for a complete description of the command portion of the TX FIFO For queued operations the SPI queues reside in system memory external to the DSPI Data transfers between the memory and...

Page 512: ...SPIx_CTARn registers select the PCSx to SCKx delay and the relationship is expressed by the following formula Table 23 23 shows an example of the computed PCS to SCK delay 23 4 7 3 After SCK Delay tAS...

Page 513: ...the DSPI is in master mode and PCSSE bit is set in the DSPIx_MCR PCSS provides a signal for an external demultiplexer to decode the PCSx 0 4 signals into as many as 32 glitch free PCSx signals Figure...

Page 514: ...ntrol the SCK signal clock polarity clock phase and number of bits to transfer must be identical for the master device and the slave device to ensure proper transmission The DSPI supports four differe...

Page 515: ...At the second edge of the SCKx the master and slave devices place their second data bit on their serial data output signals For the rest of the frame the master and the slave sample their SINx pins o...

Page 516: ...ample their SINx pins on the even numbered clock edges After the last clock edge occurs a delay of tASC is inserted before the master negates the PCSx signal A delay of tDT is inserted before a new fr...

Page 517: ...he master samples the slave SOUTx is selected by writing to the SMPL_PT field in the DSPIx_MCR Table 23 28 lists the number of system clock cycles between the active edge of SCKx and the master sample...

Page 518: ...correct operation of the modified transfer format the user must thoroughly analyze the SPI link timing budget Figure 23 33 DSPI Modified Transfer Format MTFE 1 CPHA 1 Fsck Fsys 4 23 4 8 5 Continuous...

Page 519: ...f the next transfer is the sum of tASC and tCSC i e it does not include a half clock period The default settings for these provide a total of four system clocks In many situations tASC and tCSC must b...

Page 520: ...t is set Continuous SCK is supported for modified transfer format Clock and transfer attributes for the continuous SCK mode are set according to the following rules When the DSPI is in SPI configurati...

Page 521: ...t transfer is the same as for the current transfer Figure 23 38 shows timing diagram for continuous SCK format with continuous selection enabled Figure 23 38 Continuous SCK Timing Diagram CONT 1 23 4...

Page 522: ...ueue request is generated when the EOQ bit in the executing SPI command is asserted and the EOQF_RE bit in the DSPIx_RSER is asserted See the EOQ bit description in Section 23 3 2 4 DSPI Status Regist...

Page 523: ...n request is generated when the number of entries in the RX FIFO is not zero and the RFDF_RE bit in the DSPIx_RSER is asserted The RFDF_DIRS bit in the DSPIx_RSER selects whether a DMA request or an i...

Page 524: ...its and register flags in the DSPI will return the correct values when read but writing to them will have no affect Writing to the DSPIx_TCR during module disable mode will not have any affect Interru...

Page 525: ...the CLR_RXF bit in the DSPIx_MCR 9 Clear transfer count either by setting CTCNT bit in the command word of the first entry in the new queue or via CPU writing directly to SPI_TCNT field in the DSPIx_T...

Page 526: ...TAR PBR 2 3 5 7 Baud Rate Scaler Values DSPI_CTAR BR 2 16 67 MHz 11 11 MHz 6 67 MHz 4 76 MHz 4 8 33 MHz 5 55 MHz 3 33 MHz 2 38 MHz 6 5 55 MHz 3 70 MHz 2 22 MHz 1 59 MHz 8 4 17 MHz 2 78 MHz 1 67 MHz 1...

Page 527: ...s chosen for the illustration but the concepts carry over to the RX FIFO See Section 23 4 3 4 Transmit First In First Out TX FIFO Buffering Mechanism and Section 23 4 3 5 Receive First In First Out RX...

Page 528: ...se base address of TX FIFO TXCTR TX FIFO counter TXNXTPTR transmit next pointer TX FIFO depth transmit FIFO depth 23 5 4 2 Address Calculation for the First in Entry and Last in Entry in the RX FIFO T...

Page 529: ...Deserial Serial Peripheral Interface DSPI MPC5510 Microcontroller Family Reference Manual Rev 1 23 62 Freescale Semiconductor Preliminary...

Page 530: ...e eSCI illustrates the functionality and interdependence of major blocks see Figure 24 1 Figure 24 1 eSCI Block Diagram IRQ generation Receive and wakeup control Receive shift register eSCI data regis...

Page 531: ...o operating modes of the eSCI module run mode and stop mode In run mode eSCI_x 0 in the SIU_HLT register and all functional parts of the eSCI_x module are running In stop mode eSCI_x 1 in the SIU_HLT...

Page 532: ...8000 eSCI_H 0xFFFB_C000 Register Access Reset Value Section Page 0x0000 ESCIx_CR1 eSCI control register 1 R W 0x0004_0000 24 3 2 1 24 3 0x0004 ESCIx_CR2 eSCI control register 2 R W 0xA000 24 3 2 2 24...

Page 533: ...put internally connected to transmitter output 1 Receiver input connected externally to transmitter The table below shows how LOOPS and RSRC determine the loop function of the eSCI M Data Format Mode...

Page 534: ...de 0 TC interrupt requests disabled 1 TC interrupt requests enabled RIE Receiver Full Interrupt Enable Enables the receive data register full flag ESCIx_SR RDRF and the overrun flag ESCIx_SR OR to gen...

Page 535: ...herwise cause data bytes to be interpreted as LIN header information IEBERR Enable Bit Error Interrupt Generates an interrupt when a LIN bit error is detected RXDMA Activate RX DMA Channel If this bit...

Page 536: ...Flag Interrupt Enable Generates an interrupt when noise flag is set FEIE Frame Error Interrupt Enable Generates an interrupt when a frame error is detected PFIE Parity Flag Interrupt Enable Generates...

Page 537: ...ransferred to transmit shift register transmit data register empty TC Transmit Complete Flag TC is set low when there is a transmission in progress or when a preamble or break character is loaded TC i...

Page 538: ...ty error bits 8 10 Reserved BERR Bit Error Indicates a bit on the bus did not match the transmitted bit If FBR 0 checking happens after a complete byte has been transmitted and received again If FBR 1...

Page 539: ...unchanged for 31 cycles This will reset the LIN FSM 0 No error 1 Physical bus error CERR CRC Error The CRC pattern received with an extended frame was not correct 0 No error 1 CRC error CKERR Checksu...

Page 540: ...haracter requires programming the SCI baud rate to a range of 32K baud down to 1 6K baud Refer to ESCIx_CR1 SBR field description Table 24 2 WUD Wakeup Delimiter Time Determines how long the LIN engin...

Page 541: ...n to the ESCIx_LTR will generate valid LIN frames The values are determined according to the LIN specification WUIE RX Wakeup Interrupt Enable Generates an interrupt when a wakeup flag from a LIN slav...

Page 542: ...le 24 7 W P 1 0 ID 5 0 2nd Write Table 24 8 W L 7 0 3rd Write Table 24 9 W HDCHK CSUM CRC TX RX T 11 8 4th Write Table 24 10 W T 7 0 5th Write Table 24 11 W D 7 0 Reset 0 0 0 0 0 0 0 0 Figure 24 8 LIN...

Page 543: ...wise an RX frame is assumed and the eSCI only transmits the header The data bytes are received from the slave 0 RX frame 1 TX frame Tn Timeout Bit n Sets the counter to determine a NO_RESPONSE_ERROR i...

Page 544: ...0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24 9 LIN Receive Register ESCIx_LRR Table 24 12 ESCIx_LRR Field Descriptions Field Description Dn Data Bit n Provides received data bytes fr...

Page 545: ...r operate independently although they use the same baud rate generator The CPU monitors the status of the eSCI writes the data to be transmitted and processes received data Offset Base 0x0018 Access R...

Page 546: ...ansmission and can be used repeatedly without rewriting it A frame with nine data bits has a total of 11 bits The two different data formats are illustrated in Figure 24 12 Table 24 14 and Table 24 15...

Page 547: ...he exact target frequency Table 24 16 lists some examples of achieving target baud rates with a system clock frequency of 66 MHz Table 24 14 Example of 8 bit Data Formats Start Bit Data Bits Address B...

Page 548: ...ta bit T8 in the eSCI data register ESCIx_DR is the ninth bit bit 8 0x011E 230 769 14 423 14 400 0 16 0x01AE 153 488 9 593 9 600 0 07 0x035B 76 834 4 802 4 800 0 04 0x06B7 38 394 2399 7 2 400 0 01 0x0...

Page 549: ...to enable the transmitter receiver interrupts and wakeup as required TIE TCIE RIE ILIE TE RE RWU SBK A preamble or idle character will now be shifted out of the transmitter shift register 3 Transmit...

Page 550: ...shift register 3 Queue a preamble by clearing and then setting the TE bit 4 Write the first byte of the second message to ESCIx_DR 24 4 3 3 Break Characters Setting the break bit SBK in eSCI control...

Page 551: ...ter to be lost Toggle the TE bit for a queued idle character while the TDRE flag is set and immediately before writing the next byte to the eSCI data register 24 4 3 5 Fast Bit Error Detection in LIN...

Page 552: ...ampling Figure 24 15 Fast Bit Error Detection Timing Diagram 24 4 4 Receiver Figure 24 16 illustrates the eSCI receiver Figure 24 16 eSCI Receiver Block Diagram Clock BESM13 0 BESM13 1 1 3 5 7 9 11 13...

Page 553: ...t 24 4 4 3 Data Sampling The receiver uses a sampling clock to sample the RXD input signal at the 16 times the baud rate frequency This sampling clock is called the RT clock To adjust for baud rate mi...

Page 554: ...the RT8 RT9 and RT10 start bit samples are logic 1s following a successful start bit verification the noise flag NF is set To verify a stop bit and to detect noise recovery logic takes samples at RT8...

Page 555: ...e operating at a baud rate below or above the receiver baud rate Accumulated bit time misalignment can cause one of the three stop bit data samples RT8 RT9 and RT10 to fall outside the actual stop bit...

Page 556: ...ount and the transmitter count of a slow 8 bit data character with no errors is 4 63 as is shown below For a 9 bit data character data sampling of the stop bit takes the receiver 167 RT cycles as is s...

Page 557: ...maximum percent difference between the receiver count and the transmitter count of a fast 9 bit character with no errors is 3 40 as is shown below 24 4 4 6 Receiver Wakeup The receiver can be put int...

Page 558: ...ll flag RDRF The idle line type bit ESCIx_CR1 ILT determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit 24 4 4 6 2 Address Mark Wake...

Page 559: ...o open drain See Section 6 3 2 13 Pad Configuration Registers SIU_PCR During transmission the transmitter must be enabled TE 1 the receiver may be enabled or disabled If the receiver is enabled RE 1 t...

Page 560: ...some more data to receive or transmit which does not require processor access CRC and checksum bytes or last transmit byte of a frame the eSCI will delay stop mode until these operations are complete...

Page 561: ...ister receives the next frame The newly acquired data in the shift register is lost in this case but the data already in the eSCI data registers is not affected The OR bit is cleared by writing a 1 to...

Page 562: ...ring an RX frame when the LIN slave has not transmitted all requested data bytes before the specified timeout period Writing a 1 to the bit clears the STO flag 24 4 8 2 14 PBERR Description If the RXD...

Page 563: ...n data fields n could be 0 and a checksum field The data and checksum bytes are either provided by the LIN master TX frame or by the LIN slave RX frame The header fields will always be generated by t...

Page 564: ...either using an interrupt the TX DMA interface or by polling the LIN status register If TXRDY is set the register is writable Before each write TXRDY must be checked though this step is performed auto...

Page 565: ...timeout bits which define the time to complete the entire frame must be written Then the ESCIx_SR RXRDY bit must be checked either with an interrupt RX DMA interface or by polling to detect incoming...

Page 566: ...eeds to be detected by the application software for example by setting a timer Both LIN masters and LIN slaves can cause the bus to exit sleep mode by sending a break signal The LIN hardware will gene...

Page 567: ...1 The LIN standard requires that the break character always be 13 bits long ESCIx_CR2 BRK13 1 The eSCI will work with BRK13 0 but it will violate LIN 2 0 Normally bit errors should cause the LIN FSM...

Page 568: ...nd required bandwidth The CAN protocol interface CPI submodule manages the serial communication on the CAN bus requesting RAM access for receiving and transmitting message frames validating received m...

Page 569: ...ames Zero to eight bytes data length Programmable bit rate up to 1 Mbit sec Content related addressing 64 flexible message buffers MBs of zero to eight bytes data length Each message buffer configurab...

Page 570: ...ocal priority on individual Tx message buffers Hardware cancellation on Tx message buffers Time stamp based on 16 bit free running timer Global network time synchronized by a specific message Maskable...

Page 571: ...mit and receive interrupts are generated 25 1 3 5 Module Disabled Mode This low power mode is entered when the MDIS bit in the CANx_MCR register is asserted When disabled the clocks to the CAN protoco...

Page 572: ...onfiguration R W Note1 25 3 4 1 25 11 0x0004 CANx_CTRL Control Register R W Note1 25 3 4 2 25 15 0x0008 CANx_TIMER Free running Timer R W Note1 25 3 4 3 25 18 0x000C Reserved 0x0010 CANx_RXGMASK Rx Gl...

Page 573: ...ffer structure used by the FlexCAN module is represented in Figure 25 2 Both extended and standard frames 29 bit identifier and 11 bit identifier respectively used in the CAN specification version 2 0...

Page 574: ...bit is transmitted as 0 dominant then if it is received as 1 recessive the FlexCAN module treats it as bit error If the value received matches the value transmitted it is considered as a successful bi...

Page 575: ...U reads the C S word and then unlocks the MB when a new frame is written to the MB the code returns to FULL 0110 If the code already indicates OVERRUN and yet another new frame must be written the MB...

Page 576: ...elements of the table must have the same format See Section 25 4 6 Rx FIFO for more information 0 1010 1010 Transmit a data frame whenever a remote request frame with the same ID is received This MB...

Page 577: ...Data Byte 2 Data Byte 3 0xC Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 0x10 Reserved to 0xDF 0xE0 ID Table 0 0xE4 ID Table 1 0xE8 ID Table 2 0xEC ID Table 3 0xF0 ID Table 4 0xF4 ID Table 5 0xF8...

Page 578: ...frames can be accepted and standard frames are rejected RXIDA Rx Frame Identifier foRmat A Specifies an ID to be used as acceptance criteria for the FIFO In the standard frame format only the 11 most...

Page 579: ...ure is enabled or not When FEN is set MBs 0 to 7 cannot be used for normal reception and transmission because the corresponding memory region 0x80 0xFF is used by the FIFO engine See Section 25 3 3 Rx...

Page 580: ...t be granted until current transmission and reception processes have finished Therefore the software can poll the FRZACK bit to know when FlexCAN has actually entered freeze mode If freeze mode reques...

Page 581: ...ng legacy software to work without modification 0 Individual Rx masking and queue feature are disabled 1 Individual Rx masking and queue feature are enabled bits 16 17 Reserved LPRIO_EN Local Priority...

Page 582: ...me 24 25 Reserved MAXMB Maximum Number Of Message Buffers This 6 bit field defines the maximum number of message buffers of the FlexCAN module The reset value 0x0F is equivalent to a 16 MB configurati...

Page 583: ...terrupt 0 Bus off interrupt disabled 1 Bus off interrupt enabled ERRMSK Error Mask Provides a mask for the error interrupt 0 Error interrupt disabled 1 Error interrupt enabled CLK_SRC CAN Engine Clock...

Page 584: ...bus off If BOFFREC was negated when the module entered bus off asserting it during bus off will not be effective for the current bus off recovery 0 Automatic recovering from bus off state enabled acco...

Page 585: ...cept for the fact that the data will take some time to be actually written to the register If desired software can poll the register to discover when the data was actually written 25 3 4 4 Rx Mask Reg...

Page 586: ...0 0 MB3 ID 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MB4 ID 0 0 0 0 0 0 1 1 1 1 1 0 MB5 ID 0 0 0 0 0 0 1 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MB14 ID 1 1 1 1 1 1 1 1 0 0 0...

Page 587: ...X15MASK is used as acceptance mask for the Identifier in Message Buffer 15 When the FEN bit in CANx_MCR is set FIFO enabled the CANx_RX14MASK also applies to element 7 of the ID filter table This regi...

Page 588: ...error passive and either TXECTR or RXECTR decrements to a value less than or equal to 127 while the other already satisfies this condition the FLTCONF field in the CANx_ESR is updated to reflect the e...

Page 589: ...NOTE A read clears BIT1ERR BIT0ERR ACKERR CRCERR FRMERR and STFERR therefore these bits must not be read speculatively Offset Base 0x001C Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15...

Page 590: ...detects dominant bits BIT0ERR Bit 0 Error Indicates when an inconsistency occurs between the transmitted and the received message in a bit A read clears BIT0ERR 0 No such occurrence 1 At least one bit...

Page 591: ...soft reset the FLTCONF field will not be affected by soft reset if the LOM bit is asserted 00 Error active 01 Error passive 1X Bus off bit 28 Reserved BOFFINT Bus Off Interrupt This status bit is set...

Page 592: ...rupt 0 The corresponding buffer Interrupt is disabled 1 The corresponding buffer Interrupt is enabled Note Setting or clearing a bit in the CANx_IMASK2 register can assert or negate an interrupt reque...

Page 593: ...igured as Tx the writing access done by CPU into the corresponding MB will be blocked When the FEN bit in the CANx_MCR is set FIFO enabled the function of the eight least significant interrupt flags B...

Page 594: ...lear 0 No such occurrence 1 The corresponding buffer has successfully completed transmission or reception BUF7I Buffer MB7 Interrupt or FIFO Overflow If the FIFO is not enabled this bit flags the inte...

Page 595: ...ing mechanism capable of checking incoming frames against a table of IDs up to eight extended IDs or 16 standard IDs or 32 8 bit ID slices each one with its own individual mask register Simultaneous r...

Page 596: ...entually be transmitted according to its priority At the end of the successful transmission the value of the free running timer is written into the time stamp field the code field in the control and s...

Page 597: ...he first opportunity window on the CAN bus the message on the SMB is transmitted according to the CAN protocol rules FlexCAN transmits up to eight data bytes even if the data length code DLC value is...

Page 598: ...process As a result a newly received frame matching the ID of that MB may be lost In summary never do polling by reading directly the C S word of the MBs Instead read the CANx_IFLAG registers The rec...

Page 599: ...d there When the second message arrives the matching algorithm will find MB number 2 again but it is not free to receive so it will keep looking and find MB number 5 and store the message there If yet...

Page 600: ...ule is put into freeze mode If none of conditions above are reached the MB is transmitted correctly the interrupt flag is set in the CANx_IFLAG register and an interrupt to the CPU is generated if ena...

Page 601: ...a received frame and the user deactivated the first matching MB after FlexCAN has scanned the second The received frame will be lost even if the second matching MB was free to receive If a Tx MB conta...

Page 602: ...its lock status is negated and the MB is marked as invalid for the current matching round Any pending message on the SMB will not be transferred anymore to the MB 25 4 6 Rx FIFO The receive only FIFO...

Page 603: ...he RTR bit set to 1 After the remote request frame is transmitted successfully the MB becomes a receive message buffer with the same ID as before When a remote request frame is received by FlexCAN its...

Page 604: ...CK The FlexCAN module supports a variety of means to setup bit timing parameters that are required by the CAN protocol The CANx_CTRL has various fields used to control bit timing parameters PRESDIV PR...

Page 605: ...Time Segment Syntax Syntax Description SYNCSEG System expects transitions to occur on the bus during this period Transmit Point A node in transmit mode transfers a new value to the CAN bus at this po...

Page 606: ...frequency and the CAN bit rate Figure 25 17 Arbitration Match and Move Time Windows 25 4 8 Modes of Operation Details 25 4 8 1 Freeze Mode This mode is entered by asserting the HALT bit in the CANx_M...

Page 607: ...its Rx input pin and drives its Tx pin as recessive Shuts down the clocks to the CPI and MBM submodules Sets the NOTRDY and MDISACK bits in CANx_MCR The bus interface unit continues to operate enabli...

Page 608: ...RL 25 4 10 Bus Interface The CPU access to FlexCAN registers are subject to the following rules Read and write access to unimplemented or reserved address space results in access error Any access to u...

Page 609: ...the CAN bus Note that the message buffer contents are not affected by reset so they are not automatically initialized For any configuration change initialization it is required that FlexCAN is put in...

Page 610: ...reduced version of the unified channel UC module used on MPC555x devices Each channel provides a subset of the functionality available in the unified channel at a resolution of 16 bits and provides a...

Page 611: ...nter Buses Time Bases Counter Buses Time Bases All Submodules Internal Counter Clock Enable IIB Output Disable Input 3 0 Global Time Base Enable Global Time Base Bit GTBE Output System Clock BIU IP In...

Page 612: ...e supported 26 1 3 Modes of Operation There are four main operating modes of eMIOS200 run mode module disable mode debug mode and stop mode These modes are briefly described in this section Run mode i...

Page 613: ...ed channel status and control register EMIOS_CSRn NOTE All eMIOS channels support both input and output functions When the eMIOS function is the primary function of a pin then both the input and outpu...

Page 614: ...isable input 2 emios_flag_out 9 Output disable input 1 emios_flag_out 8 Output disable input 0 Table 26 3 eMIOS200 Memory Map Offset from EMIOS_BASE 0xFFFE_4000 Register Access1 Reset Value Section Pa...

Page 615: ...1 Control Register R W 0x0000_0000 26 4 8 26 11 0x0050 EMIOS_CSR 1 Status Register R 0x0000_0000 26 4 9 26 16 0x0058 0x005F Reserved Unified Channel 2 23 Registers 0x0060 0x0031F Same as Channel 0 an...

Page 616: ...he unified channel will remain frozen until the FRZ bit is written to 0 or the MCU exits debug mode or the unified channel FREN bit is cleared 0 Exit freeze mode 1 Stops unified channel operation when...

Page 617: ...ves interrupt handling on simpler devices These bits are mirrors of the FLAG bits of each channel register EMIOS_CSR Offset EMIOS_BASE 0x0008 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14...

Page 618: ...write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 UCDIS 23 16 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R UCDIS 15 0 W Reset 0 0 0 0 0 0 0 0 0...

Page 619: ...at least one mode that requires the register is implemented then the register is present otherwise it is absent Offset UC n base address 0x0004 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13...

Page 620: ...OS200 Control Register EMIOS_CCR n The control register gathers bits reflecting the status of the unified channel input output signals and the overflow condition of the internal counter as well as sev...

Page 621: ...EDPOL for other modes but the unified channel continues to operate normally i e it continues to produce FLAG and matches When the selected output disable input signal is negated the output pin operat...

Page 622: ...n on comparator A except that the FLAG bit is not set This bit is cleared by reset and is always read as 0 This bit is valid for every output operation mode which uses comparator A otherwise it has no...

Page 623: ...modes the EDPOL bit asserts which edge triggers either the internal counter or an input capture or a FLAG When not shown in the mode of operation description this bit has no effect 0 Trigger on a fal...

Page 624: ...clock 101_0110 MCB up down counter flag on A1 match or cycle boundary internal clock 101_0111 MCB up down counter flag on A1 match or cycle boundary external clock 101_1000 OPWFMB flag on B1 match 10...

Page 625: ...22 23 24 25 26 27 28 29 30 31 R OVFL 0 0 0 0 0 0 0 0 0 0 0 0 UCIN UCOUT FLAG W w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 10 eMIOS200 Status Register EMIOS_CSR n Table 26 11 EMIOS_CSR n F...

Page 626: ...id pin transitions are received by channel Programmable input edge detector which detects the rising falling or either edges An output flip flop which holds the logic level to be applied to the output...

Page 627: ...rrent mode 26 5 1 1 1 General Purpose Input Output GPIO Mode In GPIO mode all input capture and output compare functions of the unified channel are disabled the internal counter EMIOS_CCNTR n register...

Page 628: ...gure 26 13 Single Action Input Capture Example 26 5 1 1 3 Single Action Output Compare SAOC Mode In SAOC mode a match value is loaded in register A2 and then transferred to register A1 to be compared...

Page 629: ...t When the trailing edge is detected the count value of the selected time base is latched into register A2 and at the same time the FLAG bit is set and the content of register B2 is transferred to reg...

Page 630: ...coherent data related to A2 register When EMIOS_CADR n read is performed the B1 register is loaded with the A1 register content This guarantees that the data in register B1 always has the coherent dat...

Page 631: ...registers B1 are meaningless On the second and subsequent captures the FLAG line is set and data in register B2 is transferred to register B1 When the second edge of the same polarity is detected the...

Page 632: ...red to B1 thus providing coherent data in A2 and B1 registers Transfers from B2 to B1 are then blocked until EMIOS_CBDR n is read After EMIOS_CBDR n is read register A1 content is transferred to regis...

Page 633: ...tor B MODE 6 controls if the FLAG is set on both matches or on the second match only see Table 26 10 for details If subsequent enabled output compares occur on registers A1 and B1 pulses will continue...

Page 634: ...reaches the value one The internal counter values are within a range from one up to register A1 value in MCB mode The internal counter must not reach 0x0 as consequence of a rollover To avoid this the...

Page 635: ...B mode counts between one and A1 register value Only values greater than 0x1 are allowed to be written at A1 register Loading values other than those leads to unpredictable results The counter cycle p...

Page 636: ...ate in Up Counter Mode Figure 26 25 describes the A1 register update in up down counter mode Note that A2 can be written at any time within cycle n in order to be used in cycle n 1 Thus A1 receives th...

Page 637: ...void this the user must start OPWFMB only if the value stored at internal counter is fewer than the value that EMIOS_CBDR register stores When a match on comparator A occurs the output register is set...

Page 638: ...he match signal is used to trigger the output pin transition instead of the negedge used when A1 1 A1 posedge match signal from cycle n 1 occurs at the same time as B1 negedge match signal from cycle...

Page 639: ...be used to control the update of these registers thus allowing to delay the A1 and B1 registers update for synchronization purposes In Figure 26 28 it is assumed that the channel and global prescalers...

Page 640: ...value This functionality targets applications that use active high signals and a high to low transition at A1 match In this case EDPOL should be set to 0 Cycle n Cycle n 1 Cycle n 2 A1 Value B1 Value...

Page 641: ...to the level corresponding to a match on comparators A or B respectively Similar to a B1 match FORCMB sets the internal counter to 0x000001 The FLAG bit is not set by the FORCMA or FORCMB bits being a...

Page 642: ...ntains the ideal duty cycle for the PWM signal and is compared with the selected time base Register B1 contains the dead time value and is compared against the internal counter For a leading edge dead...

Page 643: ...ip flop is set to the value of the EDPOL bit In the following match between register A1 and the selected time base the output flip flop is set to the complement of the EDPOL bit This sequence repeats...

Page 644: ...een register A1 and the selected time base the internal counter is set to 0x000001 and B1 matches are enabled When the match between register B1 and the selected time base occurs the output flip flop...

Page 645: ...dead time insertion mode lead or trail In lead dead time insertion FORCMA force a transition in the output flip flop to the opposite of EDPOL In trail dead time insertion the output flip flop is forc...

Page 646: ...suming EDPOL is set to one and OPWMCB mode with trail dead time insertion 100 duty cycle signals can be generated if B1 occurs at or after the cycle boundary external counter 1 Only values different t...

Page 647: ...es Refer to Figure 26 26 which describes the delay from matches to output flip flop transition in OPWFMB mode The operation of OPWMCB mode is similar to OPWFMB regarding matches and output pin transit...

Page 648: ...0 match from cycle n has precedence over B1 match from cycle n 1 A1 matches are masked out if they occur after B1 match within the same cycle Any value written to A2 or B2 on cycle n is loaded to A1...

Page 649: ...ycle signal Figure 26 36 OPWMB Mode with 0 Duty Cycle Figure 26 37 describes the operation of the OPWMB mode with the output disable signal asserted The output disable forces a transition in the outpu...

Page 650: ...opposite of EDPOL bit at B1 match If B1 is set to 0x000009 for instance B1 match does not occur thus a 0 duty cycle signal is generated Cycle n Cycle n 1 Cycle n 2 A1 Value B1 Value B2 Value 0x000008...

Page 651: ...opposite edge appears on the pin before validation overflow the counter is reset At the next pin transition the counter starts counting again Any pulse that is shorter than a full range of the masked...

Page 652: ...ion among all submodules and this IP interface The BIU allows 8 16 and 32 bit access They are performed over a 32 bit data bus in a single cycle clock 26 5 2 1 Effect of Freeze on the BIU When the FRZ...

Page 653: ...this procedure the first operation cycle of the selected time base can be random i e matches can occur in random time if the contents of EMIOS_CADR n or EMIOS_CBDR n were not updated with the correct...

Page 654: ...CBDR n registers to get a new measurement The FLAG indicates that new data has been captured and it is the only way to assure data coherency The FLAG set event can be detected by polling the FLAG bit...

Page 655: ...Enhanced Modular I O Subsystem eMIOS200 MPC5510 Microcontroller Family Reference Manual Rev 1 26 46 Freescale Semiconductor Preliminary...

Page 656: ...asional communication over a short distance between a number of devices It also provides flexibility allowing additional devices to be connected to the bus for further expansion and system development...

Page 657: ...at the I2 C can request data transfers with minimal support from the CPU DMA mode is enabled by setting bit 1 in the control register The DMA interface is only valid when the I2 C module is configured...

Page 658: ...tware programmable for one of 256 serial clock frequencies Software selectable acknowledge bit Interrupt driven byte by byte data transfer Arbitration lost interrupt with automatic mode switching from...

Page 659: ...ignal descriptions 27 3 Memory Map and Registers This section provides a detailed description of all I2 C registers 27 3 1 Module Memory Map Table 27 1 shows the I2 C memory map The address of each re...

Page 660: ...ss sent on the bus during the address transfer 27 3 2 2 I2 C Bus Frequency Divider Register IBFD Offset 0x00000 Access Read write any time 0 1 2 3 4 5 6 7 R AD 0 W Reset 0 0 0 0 0 0 0 0 Figure 27 3 I2...

Page 661: ...d time and the SCL Stop hold time Table 27 4 provides the SCL divider and hold values for corresponding values of the ICR The SCL divider multiplied by multiplier factor mul is used to generate I2 C b...

Page 662: ...3 158 161 09 32 7 12 17 29 384 33 190 193 0A 36 9 14 19 2A 448 65 222 225 0B 40 9 16 21 2B 512 65 254 257 0C 44 11 18 23 2C 576 97 286 289 0D 48 11 20 25 2D 640 97 318 321 0E 56 13 24 29 2E 768 129 38...

Page 663: ...the status register is also set MS Master Slave Mode Select This bit is cleared on reset When this bit is changed from 0 to 1 a START signal is generated on the bus and the master mode is selected Wh...

Page 664: ...this bit is cleared It is set by the falling edge of the ninth clock of a byte transfer This bit is valid only during or immediately following a transfer to the I2 C module or from the I2 C module 0 T...

Page 665: ...dicates the value of the R W command bit of the calling address sent from the master This bit is valid only when the I bus is in slave mode a complete address transfer has occurred with an address mat...

Page 666: ...ur parts START signal slave address transmission data transfer and STOP signal They are described briefly in the following sections and illustrated in Figure 27 10 Offset 0x0005 Access Read write any...

Page 667: ...gnal denotes the beginning of a new data transfer each data transfer may contain several bytes of data and brings all slaves out of their idle states Figure 27 11 Start and Stop conditions SCL SDA Sta...

Page 668: ...er All transfers that come after an address cycle are referred to as data transfers even if they carry sub address information for the slave device Each data byte is 8 bits long Data may be changed on...

Page 669: ...mode and stop driving the SDA output In this case the transition from master to slave mode does not generate a STOP condition Meanwhile a status bit is set by hardware to indicate loss of arbitration...

Page 670: ...or only 27 4 2 2 Interrupt Description There are five types of internal interrupts in the I2 C The interrupt service routine can determine the interrupt type by reading the status register I2 C Interr...

Page 671: ...nsmitted by selecting the master transmitter mode If the device is connected to a multi master bus system the state of the I2 C bus busy bit IBB must be tested to check if the serial bus is free If th...

Page 672: ...ster is read to determine the direction of the subsequent transfer and the TX bit is programmed accordingly For slave mode data cycles IAAS 0 the SRW bit is not valid The TX bit in the control registe...

Page 673: ...iated by writing information to IBDR for slave transmits or dummy reading from IBDR in slave receive mode The slave drives SCL low in between byte transfers SCL is released when the IBDR is accessed i...

Page 674: ...To IBDR Switch To Rx Mode Dummy Read From IBDR Generate Stop Signal Read Data From IBDR And Store Set TXAK 1 Generate Stop Signal 2nd Last Byte To Be Read Last Byte To Be Read Arbitration Lost Clear...

Page 675: ...BCR register works as a disable for the transfer complete interrupt This means that during normal transfers no errors there will always be either an interrupt or a request to the DMA controller depend...

Page 676: ...ddress is always transmitted by the CPU All subsequent data bytes apart from the two last data bytes can be read by the DMA controller The last two data bytes must be transferred by the CPU Config I2...

Page 677: ...he IBCR register The trigger to exit the DMA mode is that the programmed DMA transfer control descriptor TCD has completed all its transfers to from the I2C module Config I2C for Master TX interrupt g...

Page 678: ...via interrupt The DMA controller is programmed to signal an interrupt to the CPU which is then responsible for the deassertion of DMAEN This scheme is supported by most systems but can result in a slo...

Page 679: ...r gather process because those can result in a slow reaction Example latencies for a 32 MHz system with a full speed 32 bit AHB bus and an I2 C connected via half speed IPI bus Accessing the I2 C from...

Page 680: ...uction The PIT_RTI is an array of timers that can be used to initiate interrupts and trigger DMA channels It also provides a dedicated real time interrupt RTI timer which runs on a separate clock and...

Page 681: ...es Timers can be configured to generate interrupts instead of triggers Timers 7 and 8 can be the source of the eQADC trigger inputs via SIU configuration All interrupts are maskable and can be initiat...

Page 682: ...are disabled except the XOSC 28 2 Signal Description 28 2 1 External Signal Description The PIT_RTI module has no external signals 28 3 Memory Map and Registers This section provides a detailed descr...

Page 683: ...value register 6 R W 0x0000_0000 0x001C TLVAL7 PIT timer load value register 7 R W 0x0000_0000 0x0020 TLVAL8 PIT timer load value register 8 R W 0x0000_0000 0x0024 0x007F Reserved 0x0080 TVAL0 PIT cu...

Page 684: ...PIT Timer Load Value Register TLVAL0 TLVAL8 Table 28 3 TLVAL0 TLVAL8 Field Descriptions Field Description TSV Time Start Value Bits These bits set the timer start value The timer will count down until...

Page 685: ...0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 TIF8 TIF7 TIF6 TIF5 TIF4 TIF3 TIF2 TIF1 RTIF W w1c w1c w1c w1c w1c w1c w1c...

Page 686: ...PITINTEN Field Descriptions Field Description bits 0 22 Reserved TIEn Timer Interrupt Enable Bit 0 Interrupt requests from Timer x are disabled 1 Interrupt will be requested whenever TIFx is set When...

Page 687: ...criptions Field Description 0 22 Reserved 23 30 ISELn Interrupt Selector 0 The timer will trigger a DMA channel 1 The timer will generate an interrupt if enabled 31 Reserved Offset 0x010C Access User...

Page 688: ...e clearing the interrupt crosses clock domains a minimum value of 32 must be maintained If desired the current counter value of the timer can be read via the TVAL registers The value of the RTI counte...

Page 689: ...e Figure 28 11 Figure 28 9 Stopping and Starting a Timer Figure 28 10 Modifying Running Timer Period Figure 28 11 Dynamically Setting a New Load Value 28 4 2 Debug Mode In debug mode the timers will b...

Page 690: ...ster The timer interrupts are general purpose interrupts 28 5 Initialization and Application Information 28 5 1 Example Configuration In the example configuration The PIT clock has a frequency of 50 M...

Page 691: ...1 to bit PEN8 in the PITEN register It is also possible to set up all timers and start them simultaneously by writing to the PITEN register However the RTI still cannot start in synchronization becau...

Page 692: ...in the external address space The EBI includes a memory controller that generates interface signals to support a variety of external memories This includes single data rate SDR burst mode flash SRAM a...

Page 693: ...four chip selects In the 144 pin and 176 pin packages there are 24 address bits with only 16 bits of data and four chip selects Memory controller with support for various memory types Synchronous burs...

Page 694: ...nfiguration Register EBI_MCR for details Configurable bus speed modes and debug mode are modes that the MCU can enter in parallel to the EBI being configured in one of its module specific modes 29 1 3...

Page 695: ...rent multiplexed function e g GPIO is desired on 16 of the 32 data pins In this mode AD 16 31 are the only data signals used by the EBI by default though the user can change this to use AD 0 15 instea...

Page 696: ...ter outside EBI the EBI block completes any pending bus transactions and acknowledges the stop request After the acknowledgement the system clock input may be shut off by the clock driver on the MCU W...

Page 697: ...held until the termination of the transfer For write cycles OE is negated throughout the cycle 29 2 1 8 RD_WR Read Write RD_WR indicates whether the current transaction is a read access or a write acc...

Page 698: ...s the function and direction of the external signals in each of the EBI modes of operation The clock signals are not included because they are output only from the FMPLL module and are not affected by...

Page 699: ...description of all EBI registers 29 3 1 Module Memory Map The EBI memory map is shown in Table 29 3 The address of each register is given as an offset to the EBI base address Registers are listed in...

Page 700: ...ranch back to external flash 29 3 2 2 Separate Input Clock for Registers The EBI registers are accessed with a clock signal separate from the clock used by the rest of the EBI In module disable mode t...

Page 701: ...Table 29 4 EBI_MCR Field Descriptions Field Description bits 0 15 Reserved ACGE Automatic CLKOUT Gating Enable Enables the EBI feature of turning off CLKOUT holding it high during idle periods in bet...

Page 702: ...used for 16 bit port accesses 1 AD 16 31 signals are used for 16 bit port accesses AD_MUX Address on Data Bus Multiplexing Mode The AD_MUX bit controls whether non chip select accesses have the addre...

Page 703: ...15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R BMT BME 0 0 0 0 0 0 0 W Reset 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 Figure 29...

Page 704: ...0 16 of the internal address bus to determine if a memory bank controlled by the memory controller is being accessed by an internal bus master Note The upper 3 bits of the BA field EBI_BRn 0 2 are ti...

Page 705: ...without error based on externally asserted TA or internally asserted TA SETA should only be set when the BI bit is 1 as well since burst accesses with SETA 1 are not supported Setting SETA 1 causes th...

Page 706: ...address ranges to be used Any clear bit masks the corresponding address bit Any set bit causes the corresponding address bit to be used in comparison with the address pins Address mask bits can be set...

Page 707: ...each valid base register with 17 bits having mask See Figure 29 7 If a match is found the attributes defined for this bank in its BR and OR are used to control the memory access If a match is found in...

Page 708: ...Option Registers 0 3 EBI_ORn for a full description of all chip select attributes When no match is found on any of the chip select banks the default transfer attributes shown in Table 29 9 are used T...

Page 709: ...hort Burst Length for more detail on these cases 29 4 1 4 Bus Monitor When enabled via the BME bit in the EBI_BMCR the bus monitor detects when no TA assertion is received within a maximum timeout per...

Page 710: ...dle eight bits of the data bus AD 8 15 contain valid data during a write read cycle The lower middle write byte enable WE2 indicates that the lower middle eight bits of the data bus AD 16 23 contain v...

Page 711: ...nal devices are not required to support misaligned accesses Burst accesses internal master must be 32 bit aligned 29 4 1 13 1 Misaligned Access Support 32 bit Table 29 11 shows all the misaligned acce...

Page 712: ...fers where HUNALIGN 1 are numbered as misaligned cases The missing case numbers cannot occur on a 32 bit implementation 2 Address on internal master AHB bus not necessarily address on external ADDR pi...

Page 713: ...pled as inputs or changed as outputs with respect to that edge 29 4 2 2 Reset Upon detection of internal reset the EBI immediately terminates all transactions 8 0 Word 0x1 2 AHB transfers 00 1000 z00...

Page 714: ...4 bytes for non burst operations or a 2 beat special EBI_MCR DBM 1 case only 4 beat 8 beat or 16 beat burst of data 2 or 4 bytes per beat depending on port size when burst is enabled On a write cycle...

Page 715: ...ngle Beat Read Cycle Figure 29 10 Single Beat 32 Bit Read Cycle CS Access Zero Wait States Yes No Receives address Asserts transfer start TS drives address and attributes Master EBI Drives data Assert...

Page 716: ...ait State Figure 29 12 Single Beat 32 Bit Read Cycle Non CS Access Zero Wait States Wait state DATA is valid CLKOUT ADDR 8 31 TS DATA 0 31 TA RD_WR BDIP OE CSn DATA is valid The EBI drives address and...

Page 717: ...single beat write cycle are illustrated in the following flow and timing diagrams Figure 29 13 Basic Flow Diagram of a Single Beat Write Cycle Yes No Receives address Asserts transfer start TS drives...

Page 718: ...9 27 Preliminary Figure 29 14 Single Beat 32 Bit Write Cycle CS Access Zero Wait States Figure 29 15 Single Beat 32 Bit Write Cycle CS Access One Wait State DATA is valid CLKOUT ADDR 8 31 TS DATA 0 31...

Page 719: ...actions are independent of each other The only exceptions to this are Back to back accesses where the first access ends with an externally driven TA or TEA In these cases an extra cycle is required be...

Page 720: ...or 29 29 Preliminary Figure 29 17 Back to Back 32 Bit Reads to the Same CS Bank Figure 29 18 Back to Back 32 Bit Reads to Different CS Banks DATA is valid DATA is valid CLKOUT ADDR 8 31 TS DATA 0 31 T...

Page 721: ...10 Microcontroller Family Reference Manual Rev 1 29 30 Freescale Semiconductor Preliminary Figure 29 19 Write After Read to the Same CS Bank ADDR 8 31 TS DATA 0 31 TA RD_WR DATA is valid TSIZ 0 1 BDIP...

Page 722: ...510 Microcontroller Family Reference Manual Rev 1 Freescale Semiconductor 29 31 Preliminary Figure 29 20 Back to Back 32 Bit Writes to the Same CS Bank CLKOUT ADDR 8 31 TS DATA 0 31 TA RD_WR BDIP WE C...

Page 723: ...supports wrapping 16 byte critical doubleword first burst transfers Bursting is supported only for internally requested 16 byte read accesses to external devices that use the chip selects1 Accesses fr...

Page 724: ...port with the same burst length During burst cycles the BDIP burst data in progress signal is used to indicate the duration of the burst data During the data phase of a burst read cycle the EBI receiv...

Page 725: ...y Figure 29 22 Basic Flow Diagram of a Burst Read Cycle No Yes Receives address Asserts transfer start TS drives address and attributes Master Next to last data beat Slave Drives data Asserts transfer...

Page 726: ...to run burst cycles Using the default value of TBDIP 0 in the appropriate EBI base register results in BDIP being asserted SCY 1 cycles after the address transfer phase and being held asserted throug...

Page 727: ...t 32 bit Read Cycle One Wait State Between Beats TBDIP 1 29 4 2 6 Small Accesses Small Port Size and Short Burst Length In this context a small access refers to an access whose burst length and port s...

Page 728: ...except that multiple back to back external transfers are executed for each internal request These transfers have no additional dead cycles in between that are not present for back to back stand alone...

Page 729: ...le 2 32 byte Write with External TA Figure 29 28 shows an example of a 32 byte write to a non chip select device such as an external master using external TA requiring eight 32 bit external transactio...

Page 730: ...plitting them into multiple aligned accesses if necessary See Section 29 4 1 13 Misaligned Access Support for these cases Table 29 15 Transaction Sizes Supported by EBI No Bytes Internal Master No Byt...

Page 731: ...bus bits 0 31 and a 16 bit port must reside on bits 0 15 In the following figures and tables the following convention is adopted The most significant byte of a 32 bit operand is OP0 the least signifi...

Page 732: ...29 16 Data Bus Requirements for Read Cycles Transfer Size TSIZ 0 1 1 1 TSIZ is not enabled on the MPC5510 Address 32 Bit Port Size 16 Bit Port Size2 2 Also applies when DBM 1 for 16 bit data bus mode...

Page 733: ...k internal pullup to drive TA For EBI mastered chip select accesses when the SETA bit is 0 the EBI drives TA the entire cycle asserting according to internal wait state counters to terminate the cycle...

Page 734: ...within a reasonable period of time to avoid hanging the system When TEA is asserted from an external source the EBI uses a latched version of TEA 1 cycle delayed to help make timing at high frequencie...

Page 735: ...reads and writes so the EBI slave can internally generate one 32 bit read or write access thus 32 bit coherent as opposed to two separate 16 bit accesses Figure 29 32 shows a 32 bit non chip select r...

Page 736: ...t In such system multiplexed address data functions on AD pins are used instead of having separate address and data pins Compared to the normal EBI specification e g 24 address pins 32 data pins only...

Page 737: ...th OE negated and CS asserted to allow for the memory to three state the bus prior to the EBI driving the address on the next clock This clock gap already exists for other reasons for non small access...

Page 738: ...ta Multiplexed Bus CLKOUT ADDR 3 31 TS DATA 16 31 TA RD_WR DATA is valid TSIZ 0 1 BDIP OE CSx 10 DATA is valid Addr Addr 0x2 Addr Addr 0x2 Clock gap While the EBI drives all of ADDR 3 31 to valid addr...

Page 739: ...to SDR Burst Memory Refer to Figure 29 23 for an example of the timing of a typical burst read operation to an SDR burst memory Refer to Figure 29 14 for an example of the timing of a typical single w...

Page 740: ...r than the input setup spec 4 0 ns three wait states is sufficient If the actual input setup was less than 4 0 ns four wait states would be used instead 29 5 3 2 Timing and Connections for Asynchronou...

Page 741: ...Figure 29 38 Write Operation to Asynchronous Memory Three Initial Wait States 29 5 4 Connecting an MCU to Multiple Memories The MCU can be connected to more than one memory at a time Figure 29 39 show...

Page 742: ...or arbitration pins BB BR BG 29 5 5 1 Connecting 16 Bit MCU to 32 Bit MCU Master Master or Master Slave This scenario is straightforward Connect AD 0 15 between both MCUs and configure both for 16 bi...

Page 743: ...id chip select region 29 5 5 3 No Transfer Error TEA Pin If an MCU has no TEA pin available this eliminates the feature of terminating an access with TEA This means if an access times out in the EBI b...

Page 744: ...er CHI Controller Host Interface Cycle length in T The actual length of a cycle in T for the ideal controller 0 ppm EBI External Bus Interface FRM FlexRay Memory Memory to store message buffer payload...

Page 745: ...cs An example is the state POC normal active 30 1 4 Overview The FlexRay block is a FlexRay communication controller that implements the FlexRay Communications System Protocol Specification Version 2...

Page 746: ...n and vice versa to allow for asynchronous PE and CHI clock domains The FlexRay block stores the frame header and payload data of frames received or of frames to be transmitted in the FRM The applicat...

Page 747: ...efficient message buffer implementation Consistent data access ensured by means of buffer locking scheme Application can lock multiple buffers at the same time Size of message buffer payload data sect...

Page 748: ...pt lines One absolute timer One timer that can be configured to absolute or relative 30 1 6 Modes of Operation This section describes the basic operational power modes of the FlexRay block 30 1 6 1 Di...

Page 749: ...lexRay block signals connected to external pins These signals are summarized in Table 30 2 and described in detail in Section 30 2 1 Detailed Signal Descriptions NOTE The off chip signals FR_A_RX FR_A...

Page 750: ...tails on the debug strobe signal selection refer to Section 30 6 16 Strobe Signal Support 30 3 Controller Host Interface Clocking The clock for the CHI is derived from the system bus clock and has the...

Page 751: ...addresses presented here are the offsets relative to the FlexRay block base address which is defined by the MCU address map 1 Due to the tight timing requirements and overall system requirements of F...

Page 752: ...ister CIFRR R 0x003E System Memory Access Time Out Register SYMATOR R W Sync Frame Counter and Tables 0x0040 Sync Frame Counter Register SFCNTR R 0x0042 Sync Frame Table Offset Register SFTOR R W 0x00...

Page 753: ...ration Register MTSACFR R W 0x0082 MTS B Configuration Register MTSBCFR R W Shadow Buffer Configuration 0x0084 Receive Shadow Buffer Index Register RSBIR R W Receive FIFO Configuration 0x0086 Receive...

Page 754: ...R W 0x02F8 Message Buffer Configuration Control Status Register 63 MBCCSR63 R W 0x02FA Message Buffer Cycle Counter Filter Register 63 MBCCFR63 R W 0x02FC Message Buffer Frame ID Register 63 MBFIDR63...

Page 755: ...tten to if at least one of the conditions is fulfilled 30 5 2 2 2 Register Write Access Requirements For some of the registers a 16 bit wide write access is required to ensure correct operation This w...

Page 756: ...t read access 30 5 2 3 Module Version Register MVR This register provides the FlexRay block version number The module version number is derived from the CHI version number and the PE version number 30...

Page 757: ...rame Filtering 0 Synchronization frame filtering disabled 1 Synchronization frame filtering enabled R Reserved This bit is reserved It is read as 0 Application must not write 1 to this bit CLKSEL Prot...

Page 758: ...and FR_A_TX_EN driven by FlexRay block ports FR_B_RX FR_B_TX and FR_A_TX_EN not driven by FlexRay block PE channel 0 active uses cCrcInit B see Figure 30 134 PE channel 1 idle 1 1 reserved Table 30 1...

Page 759: ...ogic 0 For more detailed and timing information refer to Section 30 6 16 Strobe Signal Support NOTE In single channel device mode channel B related strobe signals are undefined and should not be assig...

Page 760: ...artup_state 1 for coding see PSR0 5 2 0x02 poc_startup_state 2 for coding see PSR0 6 3 0x03 poc_startup_state 3 for coding see PSR0 7 4 0x04 poc_state 0 for coding see PSR0 8 5 0x05 poc_state 1 for co...

Page 761: ...oint pulse 1 FR_A_TX 46 0x2E sync calculation complete2 pulse 47 0x2F start of offset correction pulse 2 MT start 48 0x30 cycle count 0 value 2 MT start 49 0x31 cycle count 1 50 0x32 cycle count 2 51...

Page 762: ...se 0 MT start 80 0x50 arm value 1 MT start 81 0x51 mt value 1 MT start 1 Given in PE clock cycles 2 Indicates internal PE event not directly related to FlexRay bus timing Base 0x000C Write POC config...

Page 763: ...segment correspond to the message buffer control registers MBCCSRn MBCCFRn MBFIDRn MBIDXRn with LAST_MB_SEG1 n 64 Note If LAST_MB_SEG1 63 all individual message buffers belong to the first message bu...

Page 764: ...bit controls the write mode of the POCCMD field 0 Write to POCCMD field on register write 1 Do not write to POCCMD field on register write POCCMD Protocol Control Command The application writes to th...

Page 765: ...l Interrupt Flag Register 1 PIFR1 is asserted and the related interrupt enable flag is asserted too The FlexRay block generates the combined protocol interrupt request if the PRIE flag is asserted 0 A...

Page 766: ...e or double transmit message buffers MBCCSn MTD 0 both the interrupt flag MBIF and the interrupt enable bit MBIE in the corresponding Message Buffer Configuration Control Status Registers MBCCSRn are...

Page 767: ...state immediately The fatal protocol errors are 1 pLatestTx violation as described in the MAC process of the FlexRay protocol 2 transmission across slot boundary violation as described in the FSP proc...

Page 768: ...n limit reached MXS_IF Max Sync Frames Detected Interrupt Flag This flag is set when the number of synchronization frames detected in the current communication cycle exceeds the value of the node_sync...

Page 769: ...c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 12 Protocol Interrupt Flag Register 1 PIFR1 Table 30 19 PIFR1 Field Descriptions Sheet 1 of 2 Field Description EMC_IF Error Mode...

Page 770: ...IE CCL _IE MXS _IE MTX _IE LTXB _IE LTXA _IE TBVB _IE TBVA _IE TI2 _IE TI1 _IE CYS _IE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 13 Protocol Interrupt Enable Register 0 PIER0 Table 30 20 PIER0...

Page 771: ...it controls LTXA_IF interrupt request generation 0 interrupt request generation disabled 1 interrupt request generation enabled TBVB_IE Transmission across boundary on channel B Interrupt Enable This...

Page 772: ...ration disabled 1 interrupt request generation enabled PSC_IE Protocol State Changed Interrupt Enable This bit controls PSC_IF interrupt request generation 0 interrupt request generation disabled 1 in...

Page 773: ...n Channel A Error Flag This flag is set when an overrun of the Receive FIFO for channel A occurred This error occurs if a semantically valid frame was received on channel A and matches the all criteri...

Page 774: ...the static segment as it is configured in the corresponding protocol configuration register field payload_length_static in the Protocol Configuration Register 19 PCR19 0 No such error occurred 1 Stat...

Page 775: ...ns Field Description TBIVEC Transmit Buffer Interrupt Vector This field provides the number of the lowest numbered enabled transmit message buffer that has its interrupt status flag MBIF and its inter...

Page 776: ...ble 30 25 CBSERCR Field Descriptions Field Description STATUS_ERR_CNT Channel Status Error Counter This field provides the current channel status error count The counter value is updated within the fi...

Page 777: ...erved 1010 POC coldstart consistency check 1011 reserved 1100 reserved 1101 POC integration coldstart check 1110 POC coldstart gap 1111 POC coldstart join WAKEUP STATUS Wakeup Status Protocol related...

Page 778: ...FlexRay bus while the FlexRay block was starting up the cluster 0 No such event 1 POC normal active state was reached from POC startup state via noisy leading cold start path HHR Host Halt Request Pe...

Page 779: ...Transmission conflict detected SBVB Symbol Window Boundary Violation on Channel B Protocol related variable vSS BViolation for symbol window on channel B This status bit is set if there was some medi...

Page 780: ...iled Counter Protocol related variable vClockCorrectionFailed This field provides the number of consecutive even odd communication cycle pairs that have passed without clock synchronization having per...

Page 781: ...ol was received on channel A 0 No wakeup symbol received 1 Wakeup symbol received ABVA Aggregated Boundary Violation on Channel A This flag is set when a boundary violation has been detected on channe...

Page 782: ...30 23 Macrotick Counter Register MTCTR Table 30 30 MTCTR Field Descriptions Field Description MTCT Macrotick Counter Protocol related variable vMacrotick This field provides the macrotick count of the...

Page 783: ...Counter Value for Channel B Protocol related variable vSlotCounter for channel B This field provides the number of the current slot in the current communication cycle Base 0x0038 Additional Reset RUN...

Page 784: ...om those mentioned in the Global Interrupt Flag and Enable Register GIFER Base 0x003A Additional Reset RUN Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R OFFSETCORR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 785: ...terrupt flag MBIF in the corresponding Message Buffer Configuration Control Status Registers MBCCSRn is equal to 1 0 None of the individual receive message buffers has the MBIF flag asserted 1 At leas...

Page 786: ...0 0 0 Figure 30 31 Sync Frame Counter Register SFCNTR Table 30 38 SFCNTR Field Descriptions Field Description SFEVB Sync Frames Channel B Even Cycle Protocol related variable size of vsSyncIdListB fo...

Page 787: ...s Sheet 1 of 2 Field Description ELKT Even Cycle Tables Lock Unlock Trigger This trigger bit is used to lock and unlock the even cycle tables 0 No effect 1 Triggers lock unlock of the even cycle table...

Page 788: ...set to 0 while SDVEN or SIDEN is set to 1 the FlexRay block writes continuously the enabled Sync Frame Tables into the FRM 0 Write continuously pairs of enabled Sync Frame Tables into FRM 1 Write onl...

Page 789: ...0 0 FVAL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 35 Sync Frame ID Acceptance Filter Value Register SFIDAFVR Table 30 42 SFIDAFVR Field Descriptions Field Description FVAL Filter Value This...

Page 790: ...This register defines the length of the network management vector in bytes Table 30 44 NMVR 0 5 Field Descriptions Field Description NMVP Network Management Vector Part The mapping between the Networ...

Page 791: ...r TICCR Table 30 47 TICCR Field Descriptions Field Description T2_CFG Timer T2 Configuration This bit configures the timebase mode of Timer T2 0 T2 is absolute timer 1 T2 is relative timer T2_REP Time...

Page 792: ...If the application modifies the value in this register while the timer is running the change becomes effective immediately and timer T1 will expire according to the changed value Base 0x005C Write Any...

Page 793: ...ange becomes effective when the timer has expired according to the old values 30 5 2 43 Timer 2 Configuration Register 1 TI2CR1 Base 0x0060 Write Anytime 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 T2...

Page 794: ...mapped slot status selection registers SSSR0 to SSSR3 Each internal registers selects a slot or symbol window NIT whose status vector will be saved in the corresponding Slot Status Registers SSR0 SSR...

Page 795: ...lot Number This field specifies the number of the slot whose status will be saved in the corresponding slot status registers Note If this value is set to 0 the related slot status register provides th...

Page 796: ...frames only 1 The counter is restricted to valid frames only SYF Sync Frame Restriction This bit is used to restrict the counter to received frames with the sync frame indicator bit set to 1 0 The cou...

Page 797: ...SR7 Table 30 56 SSR0 SSR7 Field Descriptions Field Description VFB Valid Frame on Channel B Protocol related variable vSS ValidFrame channel B 0 vSS ValidFrame 0 1 vSS ValidFrame 1 SYB Sync Frame Indi...

Page 798: ...or Channel A Protocol related variable vRF Header NFIndicator channel A 0 vRF Header NFIndicator 0 1 vRF Header NFIndicator 1 SUA Startup Frame Indicator Channel A Protocol related variable vRF Header...

Page 799: ...t Status Counter This field provides the current value of the Slot Status Counter Base 0x0080 Write MTE Anytime CYCCNTMSK CYCCNTVAL POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MTE 0 CYCCNTMSK 0...

Page 800: ...3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 SEL 0 0 0 0 0 RSBIDX W WMD Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 50 Receive Shadow Buffer Index Register RSBIR Table 30 60 RSBIR Field Descriptions Fie...

Page 801: ...L Controlled Receiver FIFO Registers Register Receive FIFO Start Index Register RFSIR Receive FIFO Depth and Size Register RFDSR Receive FIFO Message ID Acceptance Filter Value Register RFMIDAFVR Rece...

Page 802: ...3 4 5 6 7 8 9 10 11 12 13 14 15 R FIFO_DEPTH 0 ENTRY_SIZE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 53 Receive FIFO Depth and Size Register RFDSR Table 30 64 RFDSR Field Descriptions Field De...

Page 803: ...Value Register RFMIDAFVR This register defines the filter value for the message ID acceptance filter of the selected receive FIFO For details on message ID filtering see Section 30 6 9 5 Receive FIFO...

Page 804: ...Table 30 67 RFMIDAFVR Field Descriptions Field Description MIDAFVAL Message ID Acceptance Filter Value Filter value for the message ID acceptance filter Base 0x0092 Write POC config 0 1 2 3 4 5 6 7 8...

Page 805: ...criptions Field Description FIDRFMSK Frame ID Rejection Filter Mask Filter mask for the frame ID rejection filter Base 0x0098 16 bit write access required Write WMD IBD SEL Any Time SID POC config 0 1...

Page 806: ...filter 1 range filter 2 runs as rejection filter F1MD Range Filter 1 Mode This control bit defines the filter mode of the frame ID range filter 1 0 range filter 1 runs as acceptance filter 1 range fi...

Page 807: ...ription LASTDYNTX SLOTA Last Dynamic Transmission Slot Channel A Protocol related variable zLastDynTxSlot channel A Number of the last transmission slot in the dynamic segment for channel A If no fram...

Page 808: ...ection_passive gMaxWithoutClockCorrectionPassive cyclepairs 8 minislot_exists gNumberOfMinislots 0 0 1 bool 9 minislots_max gNumberOfMinislots 1 minislot 29 number_of_static_slots gNumberOfStaticSlots...

Page 809: ...T 19 decoding_correction_b pDecodingCorrection pDelayCompensation B 2 T 7 key_slot_header_crc header CRC for key slot 0x000 0x7FF number 12 extern_offset_correction pExternOffsetCorrection T 29 extern...

Page 810: ...3 4 5 6 7 8 9 10 11 12 13 14 15 R wakeup_symbol_rx_low minislot_action_point_offset 4 0 coldstart_attempts W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 67 Protocol Configuration Register 3 PCR3...

Page 811: ...guration Register 7 PCR7 Base 0x00B0 Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R max_without_clock_ correction_fatal max_without_clock_ correction_passive wakeup_symbol_tx_idle W Reset 0...

Page 812: ...0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 75 Protocol Configuration Register 11 PCR11 Base 0x00B8 Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R allow_passive_to_active key_slot_header_crc W Reset...

Page 813: ...0x00C0 Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R macro_initial_offset_b noise_listen_timeout 24 16 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 80 Protocol Configuration Register...

Page 814: ...A Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R extern_rate_ correction latest_tx W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 85 Protocol Configuration Register 21 PCR21 Base 0x00CC W...

Page 815: ...89 Protocol Configuration Register 25 PCR25 Base 0x00D4 Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R allow _halt_ due _to_ clock comp_accepted_startup_range_b micro_per_cycle_max 19 16 W R...

Page 816: ...ode_max W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 94 Protocol Configuration Register 30 PCR30 Base 0x0100 MBCCSR0 Base 0x0108 MBCCSR1 Base 0x02F8 MBCCSR63 Write MCM MBT MTD POC config or MB_DI...

Page 817: ...buffer is enabled i e the EDS status bit is 1 0 No effect 1 message buffer enable disable triggered Note If the application writes 1 to this bit the write access to all other bits is ignored LCKT Lock...

Page 818: ...ode of the message buffer 0 Message transferred for the first time 1 Message will be transferred again EDS Enable Disable Status This status bit indicates whether the message buffer is enabled or disa...

Page 819: ...counter filtering disabled 1 Cycle counter filtering enabled CCFMSK Cycle Counter Filtering Mask This field defines the filter mask for the cycle counter filtering CCFVAL Cycle Counter Filtering Value...

Page 820: ...used to determine the slot in which the message in this message buffer should be transmitted Base 0x0106 MBIDXR0 Base 0x010E MBIDXR1 Base 0x02FE MBIDXR63 Write POC config or MB_DIS 0 1 2 3 4 5 6 7 8...

Page 821: ...s called physical message buffers The physical message buffers are located in the FRM The structure of a physical message buffer is depicted in Figure 30 99 A physical message buffer consists of two f...

Page 822: ...detailed description of the content and usage of the slot status is provided in Section 30 6 5 2 3 Slot Status Description 30 6 2 2 Message Buffer Data Field The message buffer data field is a contigu...

Page 823: ...00 Individual Message Buffer Structure 30 6 3 1 1 Individual Message Buffer Segments The set of the individual message buffers can be split up into two message buffer segments using the Message Buffer...

Page 824: ...RSBIR RSBIDX 10 SYS_MEM_BASE_ADDR Eqn 30 4 The length required for the message buffer data field depends on the message buffer segment that the receive shadow buffer is assigned to For the receive sh...

Page 825: ...n 30 5 SADR_MBHF 1 RFSIR SIDX 10 SYS_MEM_BASE_ADDR Eqn 30 5 The start address SADR_MBHF n of the last message buffer header field that belongs to the receive FIFO in the FRM is determined according to...

Page 826: ...individual message buffers and the number of individual message buffers that are used For more details see Section 30 6 3 1 1 Individual Message Buffer Segments Specific Configuration Data The set of...

Page 827: ...MIAFMR Receive FIFO Frame ID Rejection Filter Value Register RFFIDRFVR Receive FIFO Frame ID Rejection Filter Mask Register RFFIDRFMR Receive FIFO Range Filter Configuration Register RFRFCFR 30 6 3 7...

Page 828: ...ill Equation 30 8 SADR_MBHF i 10 SYS_MEM_BASE_ADDR 0 i 1024 Eqn 30 8 3 The message buffer header fields for a receive FIFO have to be a contiguous area 30 6 4 2 Message Buffer Data Area The message bu...

Page 829: ...ge buffer header field A description of the structure of the message buffer header fields is given in Section 30 6 2 1 Message Buffer Header Field Each message buffer header field consists of three se...

Page 830: ...for frame transmission These values are generated internally before frame transmission depending on the current transmission state and configuration For transmit message buffers assigned to the stati...

Page 831: ...his is a status bit and represents the value of the Null Frame Indicator of the first valid frame received on the FlexRay bus in the slot indicated by the CYCCNT field For transmit message buffers the...

Page 832: ...this field provides the number of the communication cycle in which the frame stored in this message buffer was received For transmit message buffers the value of this field is ignored The FlexRay bloc...

Page 833: ...e Buffer see Figure 30 106 Receive FIFO Channel B Message Buffer see Figure 30 107 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R VFB SYB NFB SUB SEB CEB BVB CH VFA SYA NFA SUA SEA CEA BVA 0 Reset 0 1 2 3 4...

Page 834: ...channel that has received the first valid frame in the slot This flag is set to 0 if no valid frame was received at all in the subscribed slot 0 first valid frame received on channel A or no valid fra...

Page 835: ...UA SEA CEA BVA TCA Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 VFA SYA NFA SUA SEA CEA BVA TCA Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R VFB SYB NFB SUB SEB CEB BVB TCB 0 0 0 0 0...

Page 836: ...NFA Null Frame Indicator Channel A protocol related variable vRF Header NFIndicator channel A 0 vRF Header NFIndicator 0 1 vRF Header NFIndicator 1 SUA Startup Frame Indicator Channel A protocol relat...

Page 837: ...locked the FlexRay block will not update the Message Buffer Data Field For receive FIFOs the application can read the message buffer indicated by the Receive FIFO A Read Index Register RFARIR or the R...

Page 838: ...ocol is in the POC config state The application configures the number of utilized individual message buffers by writing the message buffer number of the last utilized message buffer into the LAST_MB_U...

Page 839: ...s disabled i e MBCCSRn EDS 0 The individual message buffer type is defined by the MTD and MBT bits in the Message Buffer Configuration Control Status Registers MBCCSRn as given in Table 30 91 The mess...

Page 840: ...ons is given in Table 30 92 If an region is active as indicated in Table 30 93 the access scheme given for that region applies to the message buffer Figure 30 112 Single Transmit Message Buffer Access...

Page 841: ...BCCSRn LCKS provide the application with the required message buffer status information The internal status information is not visible to the application 30 6 6 2 2 Message Buffer States This section...

Page 842: ...in the state CCTx the lock transition has no effect command is ignored and message buffer state is not changed In this case the message buffer lock error flag LCK_EF in the CHI Error Flag Register CHI...

Page 843: ...6 HL MBCCSRn LCKT 1 MBCCSRn LCKS 0 Application triggers message buffer lock HU MBCCSRn LCKS 1 Application triggers message buffer unlock Table 30 95 Single Transmit Message Buffer Module Transitions T...

Page 844: ...ssion As a result of the message buffer search described in Section 30 6 7 Individual Message Buffer Search the FlexRay block triggers the message available transition MA for up to two transmit messag...

Page 845: ...6 2 6 Null Frame Transmission A static slot with slot number S is assigned to the FlexRay block for channel A if at least one transmit message buffer is configured with the MBFIDRn FID set to S and MB...

Page 846: ...ted in any case even if the message buffer is unlocked or committed before the transmission slot starts A transmit message buffer timing and state change diagram for null frame transmission for this c...

Page 847: ...the MBCCFRn MTM flag is asserted the message buffer is in the state transmission mode In this case each committed message is transmitted as long as the application provides new data or locks the messa...

Page 848: ...about the slot in which the message was received A individual message buffer with message buffer number n is configured as a receive message buffer by the following configuration settings MBCCSRn MBT...

Page 849: ...the message buffer states is given in Table 30 93 which also provides the access scheme for the access regions The status bits MBCCSRn EDS and MBCCSRn LCKS provide the application with the required st...

Page 850: ...uffer is in the state CCRx the lock transition has no effect command is ignored and message buffer state is not changed In this case the message buffer lock error flag LCK_EF in the CHI Error Flag Reg...

Page 851: ...ock changes the state of up to two enabled receive message buffers from either idle state Idle or locked state HLck to the either subscribed state CCBs or locked buffer subscribed state HLckCCBs by tr...

Page 852: ...kCCRx no update will be performed The received data are lost This is indicated by setting the Frame Lost Channel A B Error Flag FRLA_EF FRLB_EF in the CHI Error Flag Register CHIERFR If a message buff...

Page 853: ...DSR MBSEG1DS the FlexRay block writes only 2 MBDSR MBSEG1DS bytes into the message buffer data field of the receive shadow buffer If the number of received bytes is less than 2 MBDSR MBSEG1DS the Flex...

Page 854: ...field must be fetched from the Message Buffer Index Registers MBIDXRn 30 6 6 4 Double Transmit Message Buffer The section provides a detailed description of the functionality of the double transmit m...

Page 855: ...it Message Buffer Access Regions Layout Table 30 103 Double Transmit Message Buffer Access Regions Description Access Description Region Type Application Module Commit Side CFG read write Message Buff...

Page 856: ...scription of the states is given in Table 30 105 The states for the transmit side of a double transmit message buffer are given in Figure 30 126 A description of the states is given in Table 30 105 Th...

Page 857: ...ked Message Buffer under configuration Commit Side can not be used for internal message transfer HLck 1 1 MSG SS Locked Applications access to data control and status Commit Side can not be used for i...

Page 858: ...that will be triggered depends on the current value of the LCKS bit The lock and unlock commands will only affect the commit side If the application triggers the lock transition HL while the commit s...

Page 859: ...on triggers message buffer disable HL MBCCSR 2n LCKT 1 MBCCSR 2n LCKS 0 Application triggers message buffer lock HU MBCCSR 2n LCKS 1 Application triggers message buffer unlock Table 30 107 Double Tran...

Page 860: ...plemented as the swapping of the content of the Message Buffer Index Registers MBIDXRn of the commit side and the transmit side After the swapping the commit side CMT bit is cleared the commit side in...

Page 861: ...is to transmit the latest data provided by the application This implies that it is not guaranteed that each provided message will be transmitted at least once The immediate commit mode is configured...

Page 862: ...ansmit side of a double transmit message buffer is the same as for single transmit message buffers which is described in Section 30 6 6 2 7 Message Buffer Status Update Additionally the slot status fi...

Page 863: ...e buffer with highest priority the message buffer with the lowest message buffer number is selected All message buffer which have the highest priority must have a consistent channel assignment as spec...

Page 864: ...e Buffer Cycle Counter Filter Registers MBCCFRn defines the channels on which the message buffer will receive or transmit The message buffer with number n transmits or receives on channel A if MBCCFRn...

Page 865: ...ion schemes 30 6 8 1 1 Basic Type Not Changed RC1 A reconfiguration will not change the basic type of the individual message buffer if both the message buffer transfer direction bit MBCCSn MTD and the...

Page 866: ...Register RFDSR 30 6 9 2 Receive FIFO Configuration The receive FIFO control and configuration data are given in Section 30 6 3 7 Receive FIFO Control and Configuration Data The configuration of the r...

Page 867: ...g to access the message buffers To access the message the application first reads the receive FIFO read index RDIDX from the Receive FIFO A Read Index Register RFARIR or Receive FIFO B Read Index Regi...

Page 868: ...ID FID that does not match the value mask filter value passes the filter i e is not rejected Consequently a received valid frame with the frame ID FID passes the RX FIFO Frame ID Value Mask Rejection...

Page 869: ...n filters i e RFRFCTR FiMD 1 and RFRFCTR FiEN 1 Equation 30 12 is fulfilled Eqn 30 12 Consequently all frames with a frame ID that fulfills Equation 30 13 for at least one of the enabled rejection fil...

Page 870: ...e both FlexRay ports are connected to physical FlexRay bus lines The FlexRay port consisting of FR_A_RX FR_A_TX and FR_A_TX_EN is connected to the physical bus channel A and the FlexRay port consistin...

Page 871: ...A is connected to a FlexRay Channel B The two FlexRay channels differ only in the initial value for the frame CRC cCrcInit For a single channel device the application can access and configure only th...

Page 872: ...fset Correction Write and Application Timing If the rate correction for the cycle pair 2n 2 2n 3 shall be affect by the external offset correction the ERC_AP field must be written to after the start o...

Page 873: ...ame ID ChA 10 Sync Frame ID ChA 11 Sync Frame ID ChA 12 Sync Frame ID ChA 13 Sync Frame ID ChA 14 Sync Frame ID ChA 15 Sync Deviation ChA 1 Sync Deviation ChA 2 Sync Deviation ChA 3 Sync Deviation ChA...

Page 874: ...his bit is set the FlexRay block will not update the table in this cycle If this bit is cleared the FlexRay block locks this table and starts the table update To indicate that these tables are current...

Page 875: ...rite the application can not lock the table that is currently written If the application locks the table outside of the table write window the lock is granted immediately 30 6 12 5 1 Sync Frame Table...

Page 876: ...transmission PCR12 key_slot_header_crc provides header crc for sync frame or startup frame Message Buffer with message buffer number n PCR18 key_slot_id The generation of the sync or startup frames d...

Page 877: ...ered for clock synchronization If a received synchronization frame did not pass at least one of the two filters this frame is processed as a normal frame and is not considered for clock synchronizatio...

Page 878: ...the following sequence 1 Write to STBSCR with WMD 1 and SEL N updates SEL field only 2 Read STBCSR The SEL field provides N and the ENB and STBPSEL fields provides the settings for signal N 30 6 16 2...

Page 879: ...rotick start event if Equation 30 25 and Equation 30 26 are fulfilled Eqn 30 25 Eqn 30 26 If the timer 1 interrupt enable bit TI1_IE in the Protocol Interrupt Enable Register 0 PIER0 is asserted an in...

Page 880: ...k start event the value of MT 31 0 is checked and then decremented Thus if the timer is started with MT 31 0 0 it expires at the next macrotick start 30 6 18 Slot Status Monitoring The FlexRay block p...

Page 881: ...going while transmission starts for slots in which the module does not transmit vSS TxConflict reception ongoing while transmission starts first valid channel that has received the first valid frame r...

Page 882: ...le The internal slot status counter is incremented if its increment condition defined by the Slot Status Counter Condition Register SSCCR matches the status vector provided by the PE All static slots...

Page 883: ...i e SSCCRn MCY 0 the internal slot status counter SSCRn_INT is reset at each cycle start If the slot status counter is in the multicycle mode i e SSCCRn MCY 1 the counter is not reset and incremented...

Page 884: ...rce has its own interrupt enable bit 30 6 19 1 5 CHI Error Interrupts The FlexRay block provides 16 interrupt sources for CHI related error events For details see CHI Error Flag Register CHIERFR There...

Page 885: ...interrupt request CHIIRQ is generated when at least one of the individual chi error interrupt sources generates an interrupt request and the interrupt enable bit GIFER CHIE is set 30 6 19 2 5 Module...

Page 886: ...MBCCSRn MBIF n CHIXIRQ 15 0 CHIER 15 0 16 PRTXIRQ 31 16 PIFR0 15 0 16 PRTXIRQ 15 0 PIFR1 15 0 16 RBIRQ CHIIRQ PRTIRQ GIFER FNEAIF FNEAIRQ GIFER WUPIF WUPIRQ GIFER RBIE MBCCSRn MTD Receive Transmit GI...

Page 887: ...mber of samples per bit cSamplesPerBit and the strobe offset cStrobeOffset The application configures the FlexRay channel bit rate by setting the BITRATE field in the Module Configuration Register MCR...

Page 888: ...initialization steps after a system reset 1 Configure FlexRay block a configure the control bits in the Module Configuration Register MCR b configure the system memory base address in System Memory B...

Page 889: ...sters MBIDXRn d configure the receive FIFOs e issue CONFIG_COMPLETE command via Protocol Operation Control Register POCR f wait for POC ready in Protocol Status Register 0 PSR0 After this sequence the...

Page 890: ...be fulfilled Eqn 30 29 This results in the formula given in Equation 30 30 which determines the required minimum CHI frequency for a given number of message buffers that are utilized Eqn 30 30 The mi...

Page 891: ...and The section considers the issues of the protocol RESET command The application issues the protocol reset command by writing the RESET command code to the POCCMD field of the Protocol Operation Con...

Page 892: ...onsidered in this section 30 7 6 1 Simple Message Buffer Configuration A simple message buffer configuration is a configuration that has at most one transmit message buffer and at most one receive mes...

Page 893: ...if there is no match on a transmit filter cycle counter filtering for example Regardless of the availability of data and the cycle counter filter the node will transmit a frame in the static slot S In...

Page 894: ...n 2 which is assigned to the receive buffer only the receive buffer will be found and the node can receive data The receive cycles are shown in Figure 30 145 Figure 30 145 Transmit Data Not Available...

Page 895: ...FlexRay Communication Controller FLEXRAY MPC5510 Microcontroller Family Reference Manual Rev 1 30 152 Freescale Semiconductor Preliminary...

Page 896: ...ip ADC is architected to allow access to all the analog channels The eQADC transfers commands from multiple command FIFOs CFIFOs to the on chip ADC The block can also receive data from the on chip ADC...

Page 897: ...he execution of commands bound for the on chip ADC It interfaces with the CFIFOs via one 2 entry command buffer CBuffer and with the RFIFOs via the result format and calibration sub block The ADC cont...

Page 898: ...t AD resolution Targets up to 9 bit accuracy at 400 KSample s ADC_CLK 6 MHz the actual accuracy is TBD subject to the final characterization Single ended signal range from 0 to 5 V Sample times of 2 d...

Page 899: ...mode If there are commands in the on chip CBuffers that were already under execution at the time the debug mode entry request is detected these commands will be completed but the generated results if...

Page 900: ...r The eQADC internal behavior after the stop mode entry request is detected differs depending on the status of the command transfer No command transfer is in progress The eQADC immediately halts futur...

Page 901: ...R0 W 31 3 3 4 31 12 0x0014 eQADC CFIFO Push Register 1 EQADC_CFPR1 W 0x0018 eQADC CFIFO Push Register 2 EQADC_CFPR2 W 0x001C eQADC CFIFO Push Register 3 EQADC_CFPR3 W 0x0020 eQADC CFIFO Push Register...

Page 902: ...Control Register 4 EQADC_IDCR4 R W 0x006A eQADC Interrupt and eDMA Control Register 5 EQADC_IDCR5 R W 0x006C Reserved 0x0070 eQADC FIFO and Interrupt Status Register 0 EQADC_FISR0 R W 31 3 3 8 31 17 0...

Page 903: ...rved 0x00A8 Reserved 0x00AC eQADC CFIFO Status Register EQADC_CFSR R 31 3 3 11 31 22 0x00B0 Reserved 0x00B4 Reserved 0x00B8 Reserved 0x00BC 0x00FC Reserved 0x0100 0x010C eQADC CFIFO0 Registers EQADC_C...

Page 904: ...0x037C Reserved 0x0380 0x038C eQADC RFIFO2 Registers EQADC_RF2Rw w 0 3 R 31 3 3 13 31 24 0x0390 0x03BC Reserved 0x03C0 0x03CC eQADC RFIFO3 Registers EQADC_RF3Rw w 0 3 R 31 3 3 13 31 24 0x03D0 0x03FC R...

Page 905: ...an edge or level gated trigger The digital filter length field specifies the minimum number of system clocks that the digital filter counter must count to recognize a logic state change Table 31 2 EQA...

Page 906: ...s that must the digital filter counter must count to recognize a logic state change The count specifies the sample period of the digital filter which is calculated according to the following equation...

Page 907: ...0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W CF_PUSHn Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 31 5 eQADC CFIFO Push Registers 0 5 EQA...

Page 908: ...0 0 0 0 0 0 0 0 0 0 0 Figure 31 6 eQADC RFIFO Pop Registers 0 5 EQADC_RFPRn Table 31 7 EQADC_RFPRn Field Descriptions Field Description bits 0 15 Reserved RF_POPn Result FIFO Pop Data n When RFIFOn is...

Page 909: ...e Writing CFINVn only invalidates commands stored in CFIFOn previously transferred commands that are waiting for execution that is commands stored in the ADC command buffer will still be executed and...

Page 910: ...d Interrupt Status Registers 0 5 EQADC_FISRn is asserted 0 Disable non coherency interrupt request 1 Enable non coherency interrupt request TORIEn Trigger Overrun Interrupt Enable n Enables the eQADC...

Page 911: ...ble CFIFO fill eDMA or interrupt request 1 Enable CFIFO fill eDMA or interrupt request Note CFFEn must not be negated while an eDMA transaction is in progress CFFSn CFIFO Fill Select n Selects if an e...

Page 912: ...1 3 3 8 eQADC FIFO and Interrupt Status Registers 0 5 EQADC_FISRn is asserted If RFDEn is asserted the eQADC generates an interrupt request when RFDSn is negated or it generates an eDMA request when R...

Page 913: ...er overrun occurred 1 Trigger overrun occurred Note The trigger overrun flag will not set for CFIFOs configured for software trigger mode PFn Pause Flag n PF behavior changes according to the CFIFO tr...

Page 914: ...the following 18 flags becomes asserted RFOFn CFUFn and TORFn assuming that all interrupts are enabled See Section 31 4 7 eQADC eDMA Interrupt Request for details Writing a 1 clears CFUFn Writing a 0...

Page 915: ...s empty 1 RFIFOn has at least one valid entry Note In the interrupt service routine RFDF must be cleared only after the RFIFOn pop register is read Note RFDFn should not be cleared when RFDSn is asser...

Page 916: ...ADC_CFTCR0 EQADC_BASE 0x0092 EQADC_CFTCR1 EQADC_BASE 0x0094 EQADC_CFTCR2 EQADC_BASE 0x0096 EQADC_CFTCR3 EQADC_BASE 0x0098 EQADC_CFTCR4 EQADC_BASE 0x009A EQADC_CFTCR5 Access Read Write 0 1 2 3 4 5 6 7...

Page 917: ...C CFIFO Status Register EQADC_CFSR captured at the time a command transfer to buffern is initiated bits 12 16 Reserved LCFT0 Last CFIFO to Transfer to ADC0 Command Buffer Holds the CFIFO number of las...

Page 918: ...gure 31 12 eQADC CFIFO Status Register EQADC_CFSR Table 31 14 EQADC_CFSR Field Descriptions Field Description CFSn CFIFO Status Indicates the current status of CFIFOn Refer to Table 31 15 for more inf...

Page 919: ...CFIFO2 Base 0x0180 CF2R0 Base 0x0184 CF2R1 Base 0x0188 CF2R2 Base 0x018C CF2R3 CFIFO3 Base 0x01C0 CF3R0 Base 0x01C4 CF3R1 Base 0x01C8 CF3R2 Base 0x01CC CF3R3 CFIFO4 Base 0x0200 CF4R0 Base 0x0204 CF4R1...

Page 920: ...R1 Base 0x0348 RF1R2 Base 0x034C RF1R3 RFIFO2 Base 0x0380 RF2R0 Base 0x0384 RF2R1 Base 0x0388 RF2R2 Base 0x038C RF2R3 RFIFO3 Base 0x03C0 RF3R0 Base 0x03C4 RF3R1 Base 0x03C8 RF3R2 Base 0x03CC RF3R3 RFI...

Page 921: ...CR is used to configure the on chip ADC Table 31 18 ADC0 Registers ADC0 Register Address Register Access Reset Value Section Page 0x0000 ADC0 Address 0x00 is used for conversion command messages 0x000...

Page 922: ...el being converted for selecting external multiplexer inputs Refer to Section 31 4 6 Internal External Multiplexing for a detailed description about how ADC0_EMUX affects channel number decoding 0 Ext...

Page 923: ...can be accessed by configuration commands sent to ADC0 0b01101 28 0b01110 30 0b01111 32 0b10000 34 0b10001 36 0b10010 38 0b10011 40 0b10100 42 0b10101 44 0b10110 46 0b10111 48 0b11000 50 0b11001 52 0...

Page 924: ...ds sent to ADC0 Table 31 21 ADC_TSCR Field Descriptions Field Description 0 11 Reserved TBC_ CLK_PS Time Base Counter Clock Prescaler Contains the system clock divide factor for the time base counter...

Page 925: ...ALUE register load the written data to the counter The time base counter counts from 0x0000 to 0xFFFF and wraps when reaching 0xFFFF Offset 0x0004 Access Read Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14...

Page 926: ...ueue one time The eQADC stops transferring commands from the triggered CFIFO after detecting the EOQ bit set in the last transfer After an EOQ bit is detected software involvement is required to rearm...

Page 927: ...C pops commands out from a CFIFO it also is checking the number of entries in the CFIFO and generating requests to fill it The process of pushing and popping commands to and from a CFIFO can occur sim...

Page 928: ...ats used for on chip ADC operation Command Queue System Memory CFIFOn ADC Priority Command Buffer 32 bits 32 bits FIFO Control Unit To ADCs eQADC DMA Transaction Done Signals Host CPU or DMAC eDMA or...

Page 929: ...FO header and an ADC result The FIFO control unit decodes the information contained in the RFIFO header to determine the RFIFO to which the ADC result should be sent An ADC result is always 16 bits lo...

Page 930: ...or continuous scan edge trigger mode 0 Do not enter WAITING FOR TRIGGER state after transfer of the current command message 1 Enter WAITING FOR TRIGGER state after transfer of the current command mes...

Page 931: ...t to the RFIFOs See Section 31 4 5 3 Time Stamp Feature for details 0 Return conversion result only 1 Return conversion time stamp after the conversion result FMT Conversion Data Format FMT specifies...

Page 932: ...he EOQ bit were asserted 1 PAUSE Pause Bit Allows software to create sub queues within a command queue When the eQADC completes the transfer of a command with an asserted pause bit the CFIFO enters th...

Page 933: ...y of the command queue Note If both the pause and EOQ bits are asserted in the same command message the respective flags are set but the CFIFO status changes as if only the EOQ bit were asserted PAUSE...

Page 934: ...obtained by executing a 2 bit left shift on the 12 bit data received from the ADC When the CAL bit is asserted this 14 bit data is the result of the calculations performed in the EQADC MAC unit using...

Page 935: ...inverted msb bit 0 0 ADC Result Figure 31 25 ADC Result Format when FMT 1 Right Justified Signed On Chip ADC Operation Table 31 29 ADC Result Format when FMT 1 Field Descriptions Field Description SI...

Page 936: ...long A CFIFO serves as a temporary storage location for the command messages stored in the command queues in system memory When a CFIFO is not full the eQADC sets the corresponding CFFF bit in Section...

Page 937: ...sh next data pointer can be calculated using the following formulas Transfer Next Data Pointer Address CFIFOn_BASE_ADDRESS TNXTPTRn 4 Push Next Data Pointer Address CFIFOn_BASE_ADDRESS TNXTPTRn CFCTRn...

Page 938: ...ailed behavior of the push next data pointer and transfer next data pointer is described in the example shown in Figure 31 28 where a CFIFO with 16 entries is shown for clarity of explanation the actu...

Page 939: ...an internal command buffer that is not full and it is the highest priority triggered CFIFO sending commands to that buffer First In Transfer Next Data Pointer Last In Push Next Data Pointer CFIFOn Tra...

Page 940: ...oritization No data from these CFIFOs will be sent to the on chip ADC nor will they stop lower priority CFIFOs from transferring commands Whenever CBuffer0 is able to receive new commands the prioriti...

Page 941: ...e falling edge or level gated external triggers The digital filter will always be active independently of the status of the MODEn field in Section 31 3 3 6 eQADC CFIFO Control Registers 0 5 EQADC_CFCR...

Page 942: ...prioritization ADC availability etc Fast and predictable transfers can be achieved by ensuring that the CFIFO is not underflowing and that the target ADC can accept commands when the CFIFO is trigger...

Page 943: ...gger mode the respective triggers are only detected when the SSS bit is asserted When the SSS bit is negated all trigger events for that CFIFO are ignored Writing a 1 to the SSE bit can be done during...

Page 944: ...SSS bit and stops transferring commands from a triggered CFIFO when an asserted EOQ bit is encountered or when CFIFO status changes from triggered due to the detection of a closed gate If a closed ga...

Page 945: ...ands start to be transferred when the CFIFO becomes the highest priority CFIFO using an available on chip ADC Although command transfers will not stop upon detection of an asserted EOQ bit at the end...

Page 946: ...onfigured into this mode No No None Continuous Scan Edge No A corresponding edge occurs Yes Yes None Continuous Scan Level No Gate is opened No No The eQADC also stops transfers from the CFIFO when CF...

Page 947: ...G FOR TRIGGER 0b10 CFIFO mode is programmed to continuous scan edge or level trigger mode OR CFIFO mode is programmed to single scan edge or level trigger mode and SSS is asserted OR CFIFO mode is pro...

Page 948: ...sserted at end of command transfer and CFIFO mode is not modified to disabled OR CFIFO in single scan level trigger mode and the gate closes while no commands are being transferred from the CFIFO and...

Page 949: ...Fn is set when the CFIFO status changes from TRIGGERED due to detection of a closed gate The pause flag interrupt routine can be used to verify if the a complete scan of the command queue was performe...

Page 950: ...detected on the last transferred command Figure 31 32 shows examples of how the eQADC would detect command sequences when transferring commands from a CFIFO Figure 31 32 Command Sequence Example The N...

Page 951: ...6 bit data from the RFIFO pop registers for every asserted eDMA request it acknowledges Refer to Section 31 5 2 eQADC eDMA Controller Interface for eDMA controller configuration guidelines Figure 31 3...

Page 952: ...data pointer n and RFCTRn is 0 When the eQADC RFIFO pop register n is read and the RFIFOn is not empty the RFIFO counter RFCTRn is decremented by 1 and the pop next data pointer is incremented by 1 or...

Page 953: ...the data in case of a null or reserved for customer use MESSAGE_TAG First In Pop Next Data Pointer Last In Receive Next Data Pointer RFIFOn Pop Next Data Pointer Receive Next Data Pointer RFIFOn Firs...

Page 954: ...ent to a disabled ADC are ignored by the ADC control hardware NOTE An 8ms wait time from VDDA power up to enabling ADC or exiting from stop or sleep mode is required to pre charge the external 100nf c...

Page 955: ...that is a time stamp is not requested the ADC returns a single result message containing the conversion result When TSR is asserted that is a time stamp is requested the ADC returns two result message...

Page 956: ...3 Quantization Error Reduction During Calibration Calibration constants GCC and OCC are determined by taking two samples of known reference voltages and using these samples to calculate their values F...

Page 957: ...n 31 5 6 3 Quantization Error Reduction During Calibration CAL_RES output is the calibrated result and it is a 14 bit unsigned value CAL_RES is truncated to 0x3FFF in case of a overflow and to 0x0000...

Page 958: ...control logic generates the proper MUX control signals and when the ADC0 1_EMUX bits are asserted the MA signals based on the channel numbers extracted from the ADC Command ADC commands are stored in...

Page 959: ...e analog input voltage sampling time set to a minimum 2 ADC clock cycles In this case the short sampling time may not allow the multiplexers to completely settle The second advantage of pipelining con...

Page 960: ...00_0000 to 0010_0111 0 to 39 VRH Single ended 0010_1000 40 VRL Single ended 0010_1001 41 MUX Settle Time and Sampling AD Conversion Minimum time necessary to perform a single conversion after channel...

Page 961: ...ence Voltage VRL For calibration of the ADC only the 25 and 75 points should be used as described in Section 31 5 6 1 MAC Configuration Procedure Table 31 37 Multiplexed Channel Assignments Input Pins...

Page 962: ...als MA0 MA1 and MA2 to select one of eight inputs These three multiplexed address signals are connected to all four external multiplexer chips The analog output of the four multiplex chips are each co...

Page 963: ...er Family Reference Manual Rev 1 31 68 Freescale Semiconductor Preliminary channel ANR ANS ANT ANW ANX ANY and ANZ by interpreting the CHANNEL_NUMBER field As a result up to 56 externally multiplexed...

Page 964: ...ing AN71 AN70 AN69 AN68 AN67 AN66 AN65 AN64 MUX 40 1 ADC0 MUX Control Logic MUX ANW ANX ANY ANZ Channel Number 0 MA2 MA1 MA0 eQADC 7 40 33 AN79 AN78 AN77 AN76 AN75 AN74 AN73 AN72 MUX AN87 AN86 AN85 AN...

Page 965: ...bit by writing a 1 to the bit End of Queue Interrupt EOQIEn 1 EOQFn 1 Clear EOQFn bit by writing a 1 to the bit Command FIFO Underflow Interrupt2 CFUIEn 1 CFUFn 1 Clear CFUFn bit by writing a 1 to th...

Page 966: ...he ADC Figure 31 42 Reference Bypass Circuit RFDEn RFDFn RFDSn RFIFO Drain Interrupt Request CFFEn CFFFn CFFSn CFIFO Fill DMA Request RFDEn RFDFn RFDSn RFIFO Drain DMA Request DMA Request Generation L...

Page 967: ...ses this sample to tell the analog module how to condition the signal The digital module also saves each successive sample and adds them according to the RSD algorithm at the end of the entire convers...

Page 968: ...es through the RSD stage Thus 13 total a and b values are collected Upon collecting all these values they will be added according to the RSD algorithm to create the 12 bit digital representation of th...

Page 969: ...Section 31 3 3 2 eQADC Null Message Send Format Register EQADC_NMSFR 3 Configure the eDMA to transfer data from Queue0 to CFIFO0 in the eQADC 4 Configure Section 31 3 3 7 eQADC Interrupt and eDMA Con...

Page 970: ...eQADC and the associated command queue structures In the example the Fast hardware triggered command queue described on the second row of Table 31 41 will have its commands transferred to ADC the conv...

Page 971: ...to generate eDMA requests to push commands into CFIFO1 and to pop result data from RFIF03 c Set CFINV1 to invalidate the contents of CFIFO1 d Set RFDE3 and CFFE1 to enable the eQADC to generate eDMA r...

Page 972: ...1 47 The location of the data to be moved is indicated by the source address and the final destination for that data by the destination address The eDMA has transfer control descriptors TCDs containin...

Page 973: ...tored The source address remains unchanged When the last expected result is written to the receive queue one of the following actions is recommended Refer to Chapter 12 Enhanced Direct Memory Access e...

Page 974: ...hen the eQADC receives a conversion result for RFIFO5 it generates an interrupt request RFIFO pop register 5 EQADC_RFPR5 can be popped to read the result Refer to Section 31 3 3 5 eQADC Result FIFO Po...

Page 975: ...CFFFn and RFDFn 8 Change MODEn to the modified CFIFO operation mode Write 1 to SSEn to trigger CFIFOn if MODEn is software trigger 31 5 5 Command Queue and Result Queue Usage Figure 31 49 is an exampl...

Page 976: ...e0 Write Command 0 No Results 0x0000 CQueue0 Read Command 1 Results to RQueue0 0x0004 CQueue0 Conversion Command 2 Results to RQueue0 0x0008 CQueue0 Conversion Command 3 Results to RQueue1 0x000C CQue...

Page 977: ...ed in the ADC calibration registers 31 5 6 1 MAC Configuration Procedure The following steps illustrate how to configure the calibration hardware that is determining the values of the gain and offset...

Page 978: ...1592 2 102 06 102 0x0066 Table 31 43 shows for this particular case examples of how the result values change according to GCC and OCC when result calibration is executed CAL 1 and when it is not CAL 0...

Page 979: ...gure 31 50 Quantization Error Reduction During Calibration threeand 4 Ideal Transfer Curve 0 Shifted Transfer Curve ADC Transfer Curve Input Voltage 12 bit A D Resolution Digital Value 14 bit Result 1...

Page 980: ...ore MMU setup with no address translation to allow the core to access all internal MCU resources and external memory address space Location and detection of user code in the internal flash Automatic s...

Page 981: ...a After the BAM has completed the boot process user code may enable the external bus interface if required 32 1 6 Serial Boot Mode This mode of operation can be used for initial MCU programming or for...

Page 982: ...e 32 3 2 BAM Program Operation If the CRP_Z1VEC register remains in its POR state the BAM code is executed after the negation of reset and before user code starts To prevent the execution of the BAM c...

Page 983: ...nloaded in serial boot mode should be compared to a fixed public value 0xFEED_FACE_CAFE_BEEF or to a flash value stored in the shadow row of internal flash at address 0x00FF_FDD8 Table 32 2 Boot Modes...

Page 984: ...cal Base Address Physical Base Address Size Attributes 0 Peripheral bridge and BAM 0xFFF0_0000 0xFFF0_0000 1 MB Big Endian Global PID 1 Internal flash 0x0000_0000 0x0000_0000 256 MB Big Endian Global...

Page 985: ...chine check exception is configured to handle possible ECC read errors that may occur while searching the internal flash to find the reset configuration halfword RCHW 32 3 3 1 1 Reset Configuration Ha...

Page 986: ...iption bits 0 4 Reserved These bit values are ignored when the halfword is read Write to 0 for future compatibility WTE Watchdog timer enable This bit determines if the MCM software watchdog timer is...

Page 987: ...uantas before the end see Figure 32 5 Figure 32 5 FlexCAN Bit Timing The eSCI is configured for one start bit eight data bits no parity and one stop bit It operates at a baud rate equal to the system...

Page 988: ...s The communication is done in half duplex manner any transmission from host is followed by the MCU transmission The host computer will not send data until it receives echo from the MCU All multibyte...

Page 989: ...dity test the MCU stops responding to all stimuli To get the MCU out of that state the RESET signal must be asserted If the password is valid the BAM refreshes the MCM software watchdog timer and perf...

Page 990: ...ll also write 0x0000 to all memory locations from the last byte of data downloaded to the following 8 byte boundary maximum 7 bytes 4 Switch to the loaded code The BAM program waits for the last echo...

Page 991: ...ked for validity and compared against stored password Platform Watchdog timer is refreshed if the password check is successful 2 32 bit store address VLE bit 31 bit number of bytes MSB first 32 bit st...

Page 992: ...are two possible interface configurations 3 pin and 5 pin In the 3 pin interface the MLBSIG and MLBDAT are bidirectional and the MLBCLK is unidirectional In the 5 pin interface all signals are unidire...

Page 993: ...ncrease flexibility MLBCLK clock adjust Visibility of debug signals 33 1 3 Modes of Operation The SoftMLB Interface Logic has two modes of operation Normal mode and Stop mode MUX DSPI_B DSPI_A MLB Sof...

Page 994: ...the signals that are multiplexed out by the SoftMLB Interface Logic In 3 pin mode the MLBCLK input MLBSIG bidirectional MLBDAT bidirectional MLBSIG_BUFEN output and MLBDAT_BUFEN output are available a...

Page 995: ...Map Offset from MLB_BASE 0xFFF8_4000 Register Access Reset Value Section Page General Registers 0x00 MLB_MCR Module Configuration Register R W 0x8000_0000 33 3 1 1 33 5 0x04 MLB_MBR MLB Blank Registe...

Page 996: ...0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33 2 MLB Module Configuration Register MLB_MCR Table 33 3 MLB Module Configuration MLB_MCR Register Field Descriptions Field Description MDIS Module Disable Controls w...

Page 997: ...t a critical interrupt to the IOP See the description of the MSVRQCIE bit below for details Note The MSYSS needs to be set before an SRV_REQ_GLUE signal will be generated 0 Interrupt request disabled...

Page 998: ...t before an SRV_REQ_CI will be generated 0 Critical interrupt request disabled default out of reset 1 Critical interrupt request enabled MIFSEL MLB Interface Select This bit selects between the 3 pin...

Page 999: ...MLB_MBR Register Field Descriptions Field Description bit 0 30 Reserved BLANK MLB Blank Request This bit is used to cancel data that has been previously queued in the DSPI FIFO due to change in the r...

Page 1000: ...his bit indicates the state of the internal eDMA request signal It is free running and high for 16 bits of the MLBCLK signal then low for the following 16 bits MDATRQS is cleared when MDIS is set MDAT...

Page 1001: ...ster RXCCHA_ACEN should only be updated when MDIS is set 0 RX Control Channel Address comparison disabled default out of reset 1 RX Control Channel Address comparison enabled bits 1 25 Reserved RXCCHA...

Page 1002: ...ister RXACHA_ACEN should only be updated when MDIS is set 0 RX Async Channel Address comparison disabled default out of reset 1 RX Async Channel Address comparison enabled bits 1 25 Reserved RXACHA RX...

Page 1003: ...ster TXCCHA_ACEN should only be updated when MDIS is set 0 TX Control Channel Address comparison disabled default out of reset 1 TX Control Channel Address comparison enabled bits 1 25 Reserved TXCCHA...

Page 1004: ...ter TXACHA_ACEN should only be updated when MDIS is set 0 TX Async Channel Address comparison disabled default out of reset 1 TX Async Channel Address comparison enabled bits 1 25 Reserved TXACHA TX A...

Page 1005: ...register TXSCHA_ACEN should only be updated when MDIS is set 0 TX Sync Channel Address comparison disabled default out of reset 1 TX Sync Channel Address comparison enabled bits 1 25 Reserved TXSCHA T...

Page 1006: ...served TXSCHAM TX Sync Channel Address Mask Register These user configuration bits are used to define bit wise masking on the TX Sync Channel address that will allow the device to recognize multiple T...

Page 1007: ...y stages enabled 0000_0000_0000_0111 3 delay stages enabled 0000_0000_0000_1111 4 delay stages enabled 0000_0000_0001_1111 5 delay stages enabled 0000_0000_0011_1111 6 delay stages enabled 0000_0000_0...

Page 1008: ...by the MLB controller INIC If the received channel address matches the programmed value in the MLB_RXICHAR register the appropriate output buffer enables are driven Section 33 4 2 1 4 MLBSIG_BUFEN and...

Page 1009: ...B_TXICHAR Field Descriptions Field Description TXICHA_ACEN TX Isochronous Channel Address Comparison Enable When enabled a received Channel Address is compared against the TX Isochronous Channel Addre...

Page 1010: ...MLB device outputs a Command Byte on its MLBSIG or MLBSO and the receiving MLB device outputs an RxStatus byte in the quadlet following the Command Byte The MLBDAT or MLBDO line is driven by the trans...

Page 1011: ...triggered by DSPI_A drain flag The second channel is used to transfer the MLBDAT values into the internal RAM triggered by the SoftMLB Interface Logic MLB_DMA_REQ and aligned with every MLB word The t...

Page 1012: ...ons The SoftMLB interface logic is enabled by asserting the MLBSIG Rx Array MLBDAT Rx Array MLBSIG Tx Word 32 bit MLBDAT Tx Word 32 bit ASYNC Frame Buffer SYNC Tx Buffer SYNC Tx Buffer eDMA pop_reg pu...

Page 1013: ...al interrupt which is Ored with the IOP external NMI An eDMA request can also be generated from the SoftMLB Interface logic This is input into the eDMA Mux input 35 and generated every 32 MLBCLK cycle...

Page 1014: ...lock the SoftMLB Interface Logic 33 4 2 1 2 MLBDAT MLBDAT is a bidirectional data line that transfers data synchronous asynchronous isochronous control to or from the network controller INIC The data...

Page 1015: ...ss the MLBSIG output buffer is enabled in the next timeslot for eight bits during the RxStatus byte field The MLBDAT output buffer is de asserted If the received Channel Address matches the programmed...

Page 1016: ...PC551xE G onto the MLB bus 33 4 2 2 5 MLBSI MLBSI receives the MLB signal from the MLB bus into the MPC551xE G 33 4 2 2 6 MLB_DATOBS and MLB_SIGOBS These signals are not part of the MLB specification...

Page 1017: ...Media Local Bus MLB MPC5510 Microcontroller Family Reference Manual Rev 1 33 26 Freescale Semiconductor Preliminary...

Page 1018: ...d 32 47 to 15 32 47 for VSSE2 in 144 pin package in Table 2 2 Corrected labels on pins 51 52 64 of 144 pin package Changed I O to O for PCS_C 0 in Table 2 1 Corrected labels on pins 52 53 in 176 pin p...

Page 1019: ...numbers in bit field names Modified text where necessary to clarify Fixed conditional text error in SIU_SRCR diagram Changed SIU_CCR figure and bit descriptions Added w1c to SIU_EISR and SIU_OSR regis...

Page 1020: ...in bit field names Modified text where necessary to clarify Various editorial changes 18 Corrected section 18 3 1 and Table 18 1 Removed superfluous bit numbers in bit field names Modified text where...

Page 1021: ...nces of IIC to I2C Amended flag bits to use w1c clearing convention 28 Removed superfluous bit numbers in bit field names Modified text where necessary to clarify Amended flag bits to use w1c clearing...

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