External Bus Interface (EBI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
29-28
Freescale Semiconductor
Preliminary
Figure 29-16. Single Beat 32-bit Write Cycle, Non-CS Access, Zero Wait States
29.4.2.4.3
Back-to-Back Accesses
Due to internal bus protocol, one dead cycle is necessary between back-to-back external bus accesses that
are not part of a set of small accesses (see
Section 29.4.2.6, “Small Accesses (Small Port Size and Short
,” for small access timing). Besides this dead cycle, in most cases, back-to-back accesses on
the external bus do not cause any change in the timing from that shown in the previous diagrams, and the
two transactions are independent of each other. The only exceptions to this are:
•
Back-to-back accesses where the first access ends with an externally-driven TA or TEA. In these
cases, an extra cycle is required between the end of the first access and the TS assertion of the
second access. See
Section 29.4.2.9, “Termination Signals Protocol
,” for more details.
NOTE
In some cases, CS remains asserted during this dead cycle, such as the cases
of back-to-back writes or read-after-write to the same chip-select. See
. The following diagrams show a few
examples of back-to-back accesses on the external bus.
DATA is valid
CLKOUT
ADDR[8:31]
TS
DATA[0:31]
TA
(Input)
RD_
WR
BDIP
WE
[0:3]
CSn
DATA is valid
The EBI drives address and control signals an extra cycle because it uses a latched
version of the external
TA
(1 cycle delayed) to terminate the cycle.
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