Clock, Reset, and Power Control (CRP)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
5-4
Freescale Semiconductor
Preliminary
is disabled and the input isolation is enabled. The RTC/API is enabled if enabled prior to entry into sleep
and stop. The voltage regulator, LVI, and power switch control are dependent on whether in sleep or stop
mode (see
Section 5.3, “Functional Description
.”)
5.2
Memory Map and Registers
This section provides a detailed description of all CRP registers.
5.2.1
Module Memory Map
The CRP memory map is shown in
. The address of each register is given as an offset to the CRP
base address. Registers are listed in address order, identified by complete name and mnemonic, and lists
the type of accesses allowed.
5.2.2
Register Descriptions
This section lists the CRP registers in address order and describes the registers and their bit fields.
Table 5-1. CRP Memory Map
Offset from
CRP_BASE
(0xFFFE_C000)
Register
Access
Reset Value
Section/Page
0x0000
CRP_CLKSRC — Clock Source Register
R/W
0x0004_DF8F
0x0004–0x000F
Reserved
0x0010
CRP_RTCSC — RTC Status and Control Register
R/W
0x0000_0000
0x0014
CRP_RTCCNT — RTC Counter Register
R
0x0000_0000
0x0018–0x003F
Reserved
0x0040
CRP_WKPINSEL — Wakeup Pin Source Select Register
R/W
0x0000_0000
0x0044
CRP_WKSE — Wakeup Source Enable Register
R/W
0x0000_0000
0x0048–0x004F
Reserved
0x0050
CRP_Z1VEC — Z1 Reset Vector Register
R/W
0xFFFF_FFFD
0x0054
CRP_Z0VEC — Z0 Reset Vector Register
R/W
0xFFFF_FFFE
0x0058
CRP_RECPTR — Recovery Pointer Register
R/W
0xFFFF_FFFC
0x005C-0x005F
Reserved
0x0060
CRP_PSCR — Power Status and Control Register
R/W
0x0000_0000
0x0064–0x006F
Reserved
0x0070
CRP_SOCSC — SoC Status and Control Register
R/W
0x0000_0000
