System Integration Unit (SIU)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
6-14
Freescale Semiconductor
Preliminary
6.3.2.3
System Reset Control Register (SIU_SRCR)
CRS
Checkstop Reset Status.
0 Last reset source the reset controller acknowledged was not an enabled checkstop reset.
1 Last reset source the reset controller acknowledged was an enabled checkstop reset.
bits 6–13
Reserved.
SSRS
Software System Reset Status.
0 Last reset source the reset controller acknowledged was not a software system reset.
1 Last reset source the reset controller acknowledged was a software system reset.
bits 15–29 Reserved.
BOOTCFG Status of BOOTCFG pin at negation of RESET.
bit 31
Reserved.
Offset:
SI 0x0010
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SSR
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
CRE0
CRE1
0
0
0
0
0
0
SSRL
0
0
0
0
0
0
0
W
Reset
1
2
1
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
The SSR bit always reads as zero. A write of zero to this bit has no effect.
2
The CRE0/1 bits are reset to 0b1 by POR. Other resets sources do not reset the bit value.
3
Once written to a 1, the SSRL bit can be reset only to zero by POR.
Figure 6-4. System Reset Control Register (SIU_SRCR)
Table 6-6. SIU_SRCR Field Descriptions
Field
Description
SSR
Software System Reset. Used to generate a software system reset. Writing a 1 to this bit causes an internal reset.
The software system reset is processed as a synchronous reset. The bit is automatically cleared on the assertion
of any other reset source except a software external reset.
0 Do not generate a software system reset.
1 Generate a software system reset.
bits 1–15
Reserved.
Table 6-5. SIU_RSR Field Descriptions (continued)
Field
Description
