System Integration Unit (SIU)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
6-3
Preliminary
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System reset monitoring and generation
— Power-on reset support
— Reset status register providing last reset source to software
— Software controlled reset assertion
•
External interrupt
— 16 interrupt requests
— Rising or falling edge event detection
— Programmable digital filter for glitch rejection
•
GPIO
— GPIO function on up to 146 I/O pins (208 BGA, number varies per package type)
— Dedicated input and output registers for each GPIO pin.
— Parallel input and output registers with pins grouped into 16-bit ports
– Read/Write data is coherent with data written/read using dedicated input/output registers.
•
Internal multiplexing
— Allows flexible selection of eQADC trigger inputs
— Allows selection of interrupt requests among external pins
— Allows selection of eMIOS inputs between external pins and deserialized DSPI outputs.
•
System clock control
— Clock divider control for individual peripherals or peripheral groups for lower power operation
— Halt request register to disable clocks to unused peripherals for lower power operation
— Halt acknowledge register to determine when peripheral clocks are disabled
6.1.3
Modes of Operation
6.1.3.1
Normal Mode
In normal mode, the SIU provides the register interface and logic that controls system configuration, the
reset controller, GPIO, clock divider control, and peripheral clock disable/acknowledge.
6.1.3.2
Debug Mode
SIU operation in debug mode is identical to normal mode operation.
