e200z1 Core (Z1)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
10-17
Preliminary
•
UR—User read permission. Allows load instructions to access the page while in user mode
(MSR[PR=1]).
•
UW—User write permission. Allows store instructions to access the page while in user mode
(MSR[PR=1]).
•
UX—User execute permission. Allows instruction fetches to access the page and instructions to be
executed from the page while in user mode (MSR[PR=1]).
If the translation match was successful, the permission bits are checked as shown in
access is not allowed by the access permission mechanism, the processor generates an Instruction or Data
Storage interrupt (ISI or DSI).
Figure 10-7. Granting of Access Permission
10.4.2
Translation Lookaside Buffer
The EIS architecture defines support for zero or more TLBs in an implementation, each with its own
characteristics, and provides configuration information for software to query the existence and structure
of the TLB(s) through a set of special purpose registers: MMUCFG, TLB0CFG, TLB1CFG, etc. By
convention, TLB0 is used for a set associative TLB with fixed page sizes, TLB1 is used for a fully
associative TLB with variable page sizes, and TLB2 is arbitrarily defined by an implementation. The
e200z1 MMU supports a single TLB which is fully associative and supports variable page sizes, thus it
corresponds to TLB1. For the rest of this document, TLB, TLBCAM, and TLB1 are used interchangeably.
The TLB consists of an 8-entry, fully associative CAM array with support for eleven page sizes. To
perform a lookup, the CAM is searched in parallel for a matching TLB entry. The contents of this TLB
entry are then concatenated with the page offset of the original effective address. The result constitutes the
real (physical) address of the access.
A hit to multiple TLB entries is considered to be a programming error. If this occurs, the TLB generates
an invalid address and TLB entries may be corrupted (an exception will not be reported).
access granted
instruction fetch
MSR[PR]
TLB_entry[UX]
TLB_entry[SX]
load-class data access
TLB_entry[UR]
TLB_entry[SR]
store-class data access
TLB_entry[UW]
TLB_entry[SW]
TLB match (see
)
