MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
23-1
Preliminary
Chapter 23
Deserial Serial Peripheral Interface (DSPI)
23.1
Introduction
The deserial serial peripheral interface (DSPI) block provides a synchronous serial interface for
communication between the MPC5510 and external devices. The DSPI supports pin-count reduction
through serialization and deserialization of eMIOS channels and memory-mapped registers. The channels
and register content are transmitted using a SPI-like protocol. There are up to four identical DSPI blocks:
DSPI_A, DSPI_B, DSPI_C, and DSPI_D; use
” to determine which
DSPI modules are available on your chosen device.
The DSPIs have three configurations:
•
Serial peripheral interface (SPI) configuration where the DSPI operates as a SPI with support for
queues.
•
Deserial serial interface (DSI) configuration where the DSPI serializes eMIOS200 output channels
and deserializes the received data by placing it on the eMIOS200 input channels.
•
Combined serial interface (CSI) configuration where the DSPI operates in both SPI and DSI
configurations interleaving DSI frames with SPI frames, giving priority to SPI frames.
NOTE
The DSPI_D deserialized outputs cannot be used as eMIOS200 input
channel signals, but can be read from a memory mapped register.
For queued operations, the SPI queues reside in system memory external to the DSPI. Data transfers
between the memory and the DSPI FIFOs are accomplished through the use of the eDMA controller or
through host software.
23.1.1
Block Diagram
is a simplified block diagram of the DSPI that illustrates the functionality and interdependence
of major blocks.
NOTE
Not all chip selects are available in the 144-pin package. For example,
DSPI_B3 and DSPI_B4 are not available. Also, owing to the multiplexing
of functions on the various pins, some chip selects may not be available if
other functions are configured to use these pins. Please pay careful attention
to your system’s pin allocation requirements.
