12. Register Descriptions
247
PowerSpan II User Manual
80A1010_MA001_09
Integrated Device Technology
www.idt.com
12.3.2
From the Processor Bus to PCI
The following PowerSpan II registers are used to generate Configuration (Type 1 or 0) and IACK
transactions going from the Processor Bus Interface to either of the PCI Interfaces:
•
PB_CONF_INFO/PB_CONF_DATA
•
PB_Px_IACK
12.3.2.1
Processor Bus Configuration Data
Generating a Configuration transaction on PCI requires the programming of the
Configuration Cycle Information Register” on page 276
(PB_CONF_INFO) to set-up the address of
the Configuration cycle. The DEST bit selects the PCI bus for the configuration access. The PCI
transaction is generated when the user performs a register access to the
Cycle Data Register” on page 279
(PB_CONF_DATA).
When a register write is performed to PB_CONF_DATA, the address and data parameters in
PB_CONF_DATA are used to generate a Configuration transaction on the selected PCI bus.
The Processor Bus Slave response to the read of PB_CONF_DATA is dependent on the state the
Address Retry Enable (ARTRY_EN) bit of the
“Processor Bus Miscellaneous Control and Status
. If ARTRY_EN is disabled, the Processor Bus slave claims the read of
PB_CONF_DATA. The Processor Bus slave only asserts PB_TA_ to complete the transaction when the
read data is returned from PCI. If ARTRY_EN is enabled, the read of PB_CONF_DATA is retried
immediately. Subsequent register accesses to PB_CONF_DATA will be retried until the data is
returned from PCI.
12.3.2.2
Interrupt Acknowledge Generation
The PB_Px_IACK registers are used to generate IACK reads on the PCI interfaces.The address for the
IACK cycle is taken directly from the processor bus.
The Processor Bus slave response to the read of PB_Px_IACK is dependent on the state of the Address
Retry Enable (ARTRY_EN) bit of the
“Processor Bus Miscellaneous Control and Status Register” on
. If ARTRY_EN is disabled, the Processor Bus slave claims the read of PB_Px_IACK. The
Processor Bus slave only asserts PB_TA_ to complete the transaction when the read data is returned
from PCI. If ARTRY_EN is enabled, the read of PB_Px_IACK is retried immediately. Subsequent
register accesses to PB_Px_IACK are retried until the data is returned from PCI.
Applications that require more than one agent to generate IACK transactions on PCI must use a
semaphore to control PB_P1_IACK and PB_P2_IACK.
Writes to PB_Px_IACK have no effect.