X20 system modules • Digital signal processing modules • X20DS1828
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X20 system User's Manual 3.10
Receiving data from a module (input)
When receiving data, the transmit array is generated by the module, transferred via FlatStream and must then
be reproduced in the receive array. The structure of the incoming data stream can be configured with the mode
register. The algorithm for receiving the data does not change in this regard.
_data_01
_data_02
_data_03
_data_04
_data_05
_data_xx
. . .
RxBytes
InputMTU must be
added to the end
of the receive array
(increase InputSequenceAck
to end properly)
If the
InputSequence
counter is increased:
Receive array
Type: USINT
InputMTU
Type: USINT
PLC / Bus controller
InputMTU is
adjusted cyclically
to the receive
buffer via X2X
_data_01
_data_02
_data_03
_data_04
_data_05
_data_xx
. . .
*TxBytes
Module-internal
transmit array
Type: USINT
Module-internal
transmit buffer
Type: USINT
Module
Cyc.
Module increases the
InputSequence counter
If permitted:
Module fills the internal
transmit buffer with the
next sequence of the
transmit array
Figure 422: FlatStream communication (input)
Algorithms
0) Cyclic status query:
- The CPU must monitor the InputSequenceCounter.
Cyclic checks:
- The module checks InputSyncAck.
- The module checks InputSequenceAck.
Preparation:
- The module forms the segments and control bytes and creates the transmit array.
Action:
- The module transfers the current element of the internal transmit array to the internal transmit buffer.
- The module increases the InputSequenceCounter.
1) Receiving (as soon as InputSequenceCounter is increased):
- The CPU must accept data from the InputMTU and append it to the end of the receive array.
- The CPU must match InputSequenceAck to the InputSequenceCounter of the sequence currently being processed.
Completion:
- The module monitors InputSequenceAck.
→ A sequence is only considered to have been transmitted successfully if it has been acknowledged via InputSequenceAck .
- Subsequent sequences are only transmitted in the next bus cycle after the completion check has been carried out successfully.
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