X20 system modules • X20 electronics module communication • X20CS1020
1554
X20 system User's Manual 3.10
Synchronization
During synchronization, a communication channel is opened. It is important to make sure that a module is present
and that the current value of the SequenceCounter is stored on the station receiving the message.
FlatStream can handle full-duplex communication. This means that both channels / communication directions can
be handled separately. They have to be synchronized independently so that simplex communication can theoret-
ically be carried out as well.
Synchronization in the output direction (CPU as the transmitter)
The corresponding synchronization bits (OutputSyncBit and OutputSyncAck) are reset. Because of this, FlatStream
cannot be used at this point in time to send messages from the CPU to the module.
Algorithm
1) The CPU must write 000 to the OutputSequenceCounter and reset the OutputSyncBit.
The CPU must cyclically query the high nibble of the "InputSequence" register (checks for 000 in OutputSequenceAck and 0 in OutputSyncAck).
The module does not accept the current contents of the InputMTU since the channel is not yet synchronized.
The module matches OutputSequenceAck and OutputSyncAck to the values of the OutputSequenceCounter and OutputSyncBit.
2) If the CPU registers the expected values in OutputSequenceAck and OutputSyncAck, it is allowed to increment the OutputSequenceCounter.
The CPU continues cyclically querying the high nibble of the "OutputSequence" register (checks for 001 in OutputSequenceAck and 0 in InputSyncAck).
The module does not accept the current contents of the InputMTU since the channel is not yet synchronized.
The module matches OutputSequenceAck and OutputSyncAck to the values of the OutputSequenceCounter and OutputSyncBit.
3) When the CPU registers the expected values in OutputSequenceAck and OutputSyncAck, it is allowed to increment the OutputSequenceCounter.
The CPU continues cyclically querying the high nibble of the "OutputSequence" register (checks for 001 in OutputSequenceAck and 1 in InputSyncAck).
Note:
Theoretically, data can be transmitted from this point forward. However, it is still recommended to wait until the output direction is completely synchronized be-
fore transmitting data.
The module sets OutputSyncAck.
The output direction is synchronized, and the CPU can transmit data to the module.
Synchronization in the input direction (CPU as the receiver)
The corresponding synchronization bits (InputSyncBit and InputSyncAck) are reset. Because of this, FlatStream
cannot be used at this point in time to send messages from the module to the CPU.
Algorithm
The module writes 000 to the InputSequenceCounter and resets the InputSyncBit.
The module monitors the high nibble of the "OutputSequence" registers and expects 000 in InputSequenceAck and 0 in InputSyncAck.
1) The CPU is not allowed to accept the current contents of the InputMTU since the channel is not yet synchronized.
The CPU has to match InputSequenceAck and InputSyncAck to the values of InputSequenceCounter and InputSyncBit.
If the module registers the expected values in InputSequenceAck and InputSyncAck, it increments the InputSequenceCounter.
The module monitors the high nibble of the "OutputSequence" registers and expects 001 in InputSequenceAck and 0 in InputSyncAck.
2) The CPU is not allowed to accept the current contents of the InputMTU since the channel is not yet synchronized.
The CPU has to match InputSequenceAck and InputSyncAck to the values of InputSequenceCounter and InputSyncBit.
If the module registers the expected values in InputSequenceAck and InputSyncAck, it sets the InputSyncBit.
The module monitors the high nibble of the "OutputSequence" register and expects 1 in InputSyncAck.
3) The CPU is allowed to set InputSyncAck.
Note:
Theoretically, data can already be transmitted in this cycle.
If the InputSyncBit is set and InputSequenceCounter has been increased by 1, the values in the enabled Rx bytes have to be accepted and acknowledged (see
also "Communication in the input direction").
The input direction is synchronized, and the module can transmit data to the CPU.
Summary of Contents for X20 System
Page 2: ......
