ISD94100 Series Technical Reference Manual
Sep 9, 2019
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FEATURES
2.1
ISD94100 Series Features
Core
–
ARM
®
Cortex
®
-M4F core running up to 200 MHz
–
Supports DSP extension with hardware divider
–
Supports IEEE 754 compliant Floating-point Unit (FPU)
–
Supports Memory Protection Unit (MPU)
–
One 24-bit system timer
–
Supports Low Power Sleepmode by WFI and WFE instructions
–
Single-cycle 32-bit hardware multiplier
–
Supports programmable 16 level priorities of Nested Vectored Interrupt Controller
(NVIC)
–
Supports programmable mask-able interrupts
–
Supports Embedded Trace Macrocell
Built-in LDO for wide operating voltage range
Flash Memory
–
Up to 512KB on-chip Application ROM (APROM)
–
Configurable program code/data allocation
–
4 KB Flash for loader (LDROM)
–
Supports 2-wire ICP update through SWD/ICE interface
–
Supports In-system program (ISP), In application program (IAP) update
–
Supports 4 KB page erase for all embedded flash
–
Supports 4 KB two-way cache to reduce power consumption and improve
performance.
–
Enhanced performance up to 3.4 Core Mark/MHz when running code in Flash with
cache
–
Supports 2-wire ICP flash updating through SWD interface
–
Supports 32-bit/64-bit and multi-word flash programming function.
–
Supports fast flash programming verification by CRC function.
SRAM
–
Up to 192 KB embedded SRAM
–
32 KB SRAM in bank 0 that supports hardware parity check and retention mode
–
Supports byte-, half-word- and word-access
–
Supports exception (NMI) generated once a parity check error occurs
–
Supports PDMA mode
Clock Control
–
Built-in 48.0 MHz or 49.152 MHz selectable internal high speed RC oscillator (HIRC) for
system operation
–
Built-in 10 kHz internal low speed RC oscillator (LIRC) for Watchdog Timer and wake-
up operation
–
4~24.576 MHz external high speed crystal oscillator (HXT) for precise timing operation
–
32.768 kHz external low speed crystal oscillator (LXT) for RTC function and low-power
