ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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Power-on Reset Controller Register (SYS_PORCTL)
Register
Offset
R/W Description
Reset Value
SYS_PORCTL
0x24
R/W Power-On-Reset Controller Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
POROFF
7
6
5
4
3
2
1
0
POROFF
Bits
Description
[31:16]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[15:0]
POROFF
Power-on Reset Enable Bit (Write Protected)
When power is applied to device, the POR circuit generates a reset signal to reset the entire
chip function. Noise on the power may cause the POR to become active again. User can
disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing
0x5AA5 to this field.
The POR function will be active again when this field is set to another value or chip is reset
by other reset source, including:
nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset
function.
Note:
This bit is write protected. Refer to the SYS_REGLCTL register.
