ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Each block is described in detail as follows:
TX_FIFO
The transmitter is buffered with a 16 bytes FIFO to reduce the number of interrupts presented to
the CPU.
RX_FIFO
The receiver is buffered with a 16 bytes FIFO (plus three error bits, BIF (UART_FIFOSTS[6]), FEF
(UART_FIFOSTS[5]), PEF (UART_FIFOSTS[4])) to reduce the number of interrupts presented to
the CPU.
TX Shift Register
This block is responsible for shifting out the transmitting data serially.
RX Shift Register
This block is responsible for shifting in the receiving data serially.
Modem Control and Status Register
This register controls the interface to the MODEM or data set (or a peripheral device emulating a
MODEM).
Baud Rate Generator
Divide the external clock by the divisor to get the desired baud rate clock. Refer to baud rate
equation.
FIFO & Line Control and Status Register
This field is register set that including the FIFO control register (UART_FIFO), FIFO status
register (UART_FIFOSTS), and line control register (UART_LINE) for transmitter and receiver.
The time-out register (UART_TOUT) identifies the condition of time-out interrupt.
Auto-Baud Rate Measurement
This block is responsible for auto-baud rate measurement.
Interrupt Control and Status Register
There are ten types of interrupts, shown in Table 6.12.3-1. Write into UART Interrupt Enable
Register (UART_INTEN) to enable/disable interrupt(s), and check UART Interrupt Status Register
(UART_INTSTS) to identify the source of a UART interrupt.
Interrupt
Description
RDAINT
Receive Data Available Interrupt.
THERINT
Transmit Holding Register Empty Interrupt.
TXENDINT
Transmitter Empty Interrupt.
