ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Data bit is latched on positive edge of SPI bus clock.
Data bit is driven on negative edge of SPI bus clock.
Data is transferred from LSB first.
SPI bus clock is idle at high state.
Only one byte of data to be transmitted/received in a transaction.
Slave selection signal is active high.
The operation flow is as follows:
1) Write the SPIn_SSCTL register a proper value for the related settings of Slave mode.
Select high level for the input of slave selection signal by setting SSACTPOL (SPIn_SSCTL[2])
to 1.
2) Write the related settings into the SPIn_CTL register to control this SPI slave actions
1. Set the SPI controller as slave device by setting SLAVE (SPIn_CTL[18]) to 1.
2. Select the SPI clock idle state at high by setting CLKPOL (SPIn_CTL[3]) to 1.
3. Select data transmitted on negative edge of SPI bus clock by setting TXNEG
(SPIn_CTL[2]) to 1.
4. Select data latched on positive edge of SPI bus clock by clearing RXNEG (SPIn_CTL[1])
to 0.
5. Set the bit length of a transaction as 8-bit in DWIDTH bit field (SPIn_CTL[12:8] = 0x08).
6. Set LSB transfer first by setting LSB (SPIn_CTL[13]) to 1.
3) Set the SPIEN (SPIn_CTL[0]) to 1. Wait for the slave select trigger input and SPI clock input
from the off-chip master device to start the data transfer.
4) If this SPI slave attempts to transmit (be read) one byte data to the off-chip master device,
write the byte data that will be transmitted into the SPIn_TX register.
5) If this SPI slave just only attempts to receive (be written) one byte data from the off-chip
master device and does not care what data will be transmitted, the SPIn_TX register does
not need to be updated by software.
6) Waiting for SPI interrupt if the UNITIEN (SPIn_CTL[17]) is set to 1, or just polling the unit
transfer interrupt flag UNITIF (SPIn_STATUS[1]).
7) Read out the received one byte data from SPIn_RX register.
8) Go to 4) to continue another data transfer or stop data transfer.
