ISD94100 Series Technical Reference Manual
Sep 9, 2019
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DMIC FIFO Data Output Register (DMIC_FIFO)
Register
Offset
R/W Description
Reset Value
DMIC_FIFO
0x10
W
DMIC FIFO Data Output Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
FIFO
15
14
13
12
11
10
9
8
FIFO
7
6
5
4
3
2
1
0
FIFO
Bits
Description
[31:24]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write
with reset value.
[23:0]
FIFO
FIFO Data Output Register
DMIC contains 32 words (32x32 bit) data buffer for data receive. A read to this register
pushes data out from FIFO data buffer and decrements the read pointer. This is the
address that PDMA reads audio data from. The remaining data word number is indicated
by FIFOPTR (DMIC_STATUS[8:4]).
