ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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DMIC Status Register (DMIC_STATUS)
Register
Offset
R/W Description
Reset Value
DMIC_STATUS
0x08
R
DMIC Status Register
0x0000_0002
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
FIFOPTR
7
6
5
4
3
2
1
0
FIFOPTR
Reserved
THIF
EMPTY
FULL
Bits
Description
[31:9]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write
with reset value.
[8:4]
FIFOPTR
FIFO Pointer (Read Only)
The FULL (DMIC_STATUS[0]) and FIFOPTR (DMIC_STATUS[8:4]) indicates the field
that the valid data count within the DMIC FIFO buffer.
The maximum value shown in FIFOPTR (DMIC_STATUS[8:4]) is 31. When the using
level of DMIC FIFO buffer equal to 32, The FULL (DMIC_STATUS[0]) is set to 1.
[3]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write
with reset value.
[2]
THIF
FIFO Threshold Interrupt Status (Read Only)
0 = The valid data count within the FIFO data buffer is less than the setting value of TH
(DMIC_DIV[20:16]).
1 = The valid data count within the FIFO data buffer is more than or equal to the setting
value of TH (DMIC_DIV[20:16]).
[1]
EMPTY
FIFO Empty Indicator (Read Only)
0 = FIFO is not empty.
1 = FIFO is empty.
[0]
FULL
FIFO Full Indicator (Read Only)
0 = FIFO is not full.
1 = FIFO is full.
