ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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ADC Double Data Register n for Sample Module n (EADC_DDAT0~3)
Register
Offset
R/W Description
Reset Value
EADC_DDAT0
0x100
R
ADC Double Data Register 0 for Sample Module 0
0x0000_0000
EADC_DDAT1
0x104
R
ADC Double Data Register 1 for Sample Module 1
0x0000_0000
EADC_DDAT2
0x108
R
ADC Double Data Register 2 for Sample Module 2
0x0000_0000
EADC_DDAT3
0x10C
R
ADC Double Data Register 3 for Sample Module 3
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
VALID
OV
15
14
13
12
11
10
9
8
RESULT
7
6
5
4
3
2
1
0
RESULT
Bits
Description
[31:17]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[17]
VALID
Valid Flag
0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid.
1 = Double data in RESULT (EADC_DDATn[15:0]) is valid.
This bit is set to 1 when corresponding sample module channel analog input conversion is
completed and cleared by hardware after EADC_DDATn register is read. (n=0~3).
[16]
OV
Overrun Flag
0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result.
1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite.
If converted data in RESULT[15:0] has not been read before new conversion result is
loaded to this register, OV is set to 1. It is cleared by hardware after EADC_DDAT register
is read.
[15:0]
RESULT
ADC Conversion Results
This field contains 12 bits conversion results.
When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned
format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].
When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2’complement
format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12].
