ISD94100 Series Technical Reference Manual
Sep 9, 2019
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of 928
Rev1.09
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S
ER
IE
S
T
E
C
HN
ICA
L
RE
F
E
RE
NCE
M
AN
U
AL
This timing parameter covers the condition where a master has been dynamically added to the bus
and may not have detected a state transition on the SMBCLK or SMBDAT lines. In this case, the
master must wait long enough to ensure that a transfer is not currently in progress. The peripheral
supports a hardware bus idle detection.
6.13.5.3 Programmable setup and hold times
In order to guarantee a correct data setup and hold time, the timing must be configured. By
programming HTCTL [5:0] (I2C_TMCTL[11:6]) to configure hold time and STCTL [5:0]
(I2C_TMCTL[5:0]) to configure setup time.
The delay timing refer peripheral clock (PCLK). When device stretch master clock, the setup and
hold time configuration value will not affected by stretched.
User should focus the limitation of setup and hold time configuration, the timing setting must follow
I
2
C protocol. Once setup time configuration greater than design limitation, that means if setup time
setting make SCL output less than three PCLKs, I
2
C controller can’t work normally due to SCL must
sample three times. And once hold time configuration greater than I
2
C clock limitation, I
2
C will occur
bus error. Suggest that user calculate suitable timing with baud rate and protocol before setting
timing. Table 6.13.5-2 shows the relationship between I
2
C baud rate and PCLK, the number of table
represent one clock duty contain how many PCLKs. Setup and hold time configuration even can
program some extreme values in our design, but user should follow I
2
C protocol standard.
I
2
C Baud Rate
PCLK
100k
200k
400k
800k
1200k
12 MHz
120
60
30
15
10
24 MHz
240
120
60
30
20
48 MHz
480
240
120
60
40
72 MHz
720
360
180
90
60
Table 6.13.5-2 Relationship between I
2
C Baud Rate and PCLK
For setup time wrong adjustment example, we assume one SCL cycle contains 5 PCLKs and set
STCTL [5:0] (I2C_TMCTL[5:0]) to 3 that stretch three PCLKs for setup time setting. The setup time
setting limitation:
ST
limit
= (I2C_CLKDIV[7:0]+1) X 2 - 6.
SCL_OUT
PCLK
Only two PCLKs
. . . . . .
. . . . . .
Two PCLKs can not sample three times
