ISD94100 Series Technical Reference Manual
Sep 9, 2019
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memory mapped devices, access to internal core registers when the core is
halted, and access to debug control registers even while SYSRESETn is asserted.
Serial Wire Debug Port(SW-DP) debug access
Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and
code patches
Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints,
data tracing, and system profiling
Optional Instrumentation Trace Macrocell (ITM) for support of printf() style
debugging
Optional Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
(TPA), including Single Wire Output (SWO) mode
Bus interfaces:
Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, Dcode,
and System bus interfaces
Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB) interface
Bit-band support that includes atomic bit-band write and read operations.
Memory access alignment
Write buffer for buffering of write data
Exclusive access transfers for multiprocessor systems
