ISD94100 Series Technical Reference Manual
Sep 9, 2019
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RXOFF (UART_FIFO [8]) then enable RS485NMM (UART_ALTCTL[8]) and the receiver will
received any data.
If an address byte is detected (bit 9 = 1), it will generate an interrupt to CPU and RXOFF
(UART_FIFO[8]) can decide whether accepting the following data bytes are stored in the RX FIFO.
If software disables receiver by setting RXOFF (UART_FIFO[8]) register, when a next address byte
is detected, the controller will clear the RXOFF (UART_FIFO[8]) bit and the address byte data will
be stored in the RX FIFO.
RS-485 Auto Address Detection Operation Mode
(AAD)
In RS-485 Auto Address Detection Operation Mode (RS485AAD (UART_ALTCTL[9]) = 1), the
receiver will ignore any data until an address byte is detected (bit 9 = 1) and the address byte data
matches the ADDRMV (UART_ALTCTL[31:24]) value. The address byte data will be stored in the
RX FIFO. The all received byte data will be accepted and stored in the RX FIFO until an address
byte data not match the ADDRMV (UART_ALTCTL[31:24]) value.
RS-485 Auto Direction Function
(AUD)
Another option function of RS-485 controllers is RS-485 auto direction control function (RS485AUD
(UART_ALTCTL[10) = 1). The RS-485 transceiver control is implemented by using the nRTS
control signal from an asynchronous serial port. The nRTS line is connected to the RS-485
transceiver enable pin such that setting the nRTS line to high (logic 1) enables the RS-485
transceiver. Setting the nRTS line to low (logic 0) puts the transceiver into the tri-state condition to
disabled. User can set RTSACTLV in UART_MODEM register to change the nRTS driving level.
Figure 6.12-15 demonstrates the RS-485 nRTS driving level in AUD mode. The nRTS pin will be
automatically driven during TX data transmission.
Setting RTSACTLV(UART_MODEM[9]) can control nRTS pin output driving level. User can read
the RTSSTS(UART_MODEM[13]) bit to get real nRTS pin output voltage logic status.
