ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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I2S Status Register 0 (I2S_STATUS0)
Register
Offset
R/W Description
Reset Value
I2S_STATUS0
0x0C
R/W I
2
S Status Register 0
0x0014_1000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
TXBUSY
TXEMPTY
TXFULL
TXTHIF
TXOVIF
TXUDIF
15
14
13
12
11
10
9
8
Reserved
RXEMPTY
RXFULL
RXTHIF
RXOVIF
RXUDIF
7
6
5
4
3
2
1
0
Reserved
DATACH
I2STXINT
I2SRXINT
I2SINT
Bits
Description
[31:22]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[21]
TXBUSY
Transmit Busy (Read Only)
0 = Transmit shift buffer is empty.
1 = Transmit shift buffer is busy.
Note:
This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out.
And set to 1 when 1
st
data is load to shift buffer.
[20]
TXEMPTY
Transmit FIFO Empty (Read Only)
This bit reflect data word number in transmit FIFO is zero
0 = Not empty.
1 = Empty.
[19]
TXFULL
Transmit FIFO Full (Read Only)
This bit reflect data word number in transmit FIFO is 16
0 = Not full.
1 = Full.
[18]
TXTHIF
Transmit FIFO Threshold Interrupt Flag (Read Only)
0 = Data word(s) in FIFO is higher than threshold level.
1 = Data word(s) in FIFO is equal or lower than threshold level.
Note:
When data word(s) in transmit FIFO is equal to or lower than threshold value set in
TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1. It keeps at 1 till TXCNT
(I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO
register.
[17]
TXOVIF
Transmit FIFO Overflow Interrupt Flag
0 = No overflow.
1 = Overflow.
Note1:
Write data to transmit FIFO when it is full and this bit set to 1
Note2:
Write 1 to clear this bit to 0.
