ISD94100 Series Technical Reference Manual
Sep 9, 2019
Page
741
of 928
Rev1.09
IS
D
9
410
0
S
ER
IE
S
T
E
C
HN
ICA
L
RE
F
E
RE
NCE
M
AN
U
AL
I2S Clock Divider Control Register (SPIn_I2SCLK)
Register
Offset
R/W Description
Reset Value
SPI1_I2SCLK
0x64
R/W SPI1 I
2
S Clock Divider Control Register
0x0000_0000
SPI2_I2SCLK
0x64
R/W SPI2 I
2
S Clock Divider Control Register
0x0000_0000
Note:
Not supported in SPI mode.
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
BCLKDIV
15
14
13
12
11
10
9
8
BCLKDIV
7
6
5
4
3
2
1
0
Reserved
MCLKDIV
Bits
Description
[31:18]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[17:8]
BCLKDIV
Bit Clock Divider
The I
2
S controller will generate bit clock in Master mode. The clock frequency of bit clock ,
f
BCLK
, is determined by the following expression:
)
1
BCLKDIV
(
2
_
_
2
+
×
=
f
f
src
clock
s
i
BCLK
where
f
src
clock
s
i
_
_
2
is the frequency of I
2
S peripheral clock source, which is defined in the
clock control register CLK_CLKSEL2.
In I
2
S Slave mode, this field is used to define the frequency of peripheral clock and it’s
determined by
+
÷
1
2
BCLKDIV
_
_
2
f
src
clock
s
i
.
The peripheral clock frequency in I
2
S Slave mode must be equal to or faster than 6 times of
input bit clock.
Note: User should set BCLKDIV carefully because the peripheral clock frequency
must be slower than or equal to system frequency
[7]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
