ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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HIRC Trim Interrupt Enable Register (SYS_IRCTIEN)
Register
Offset
R/W Description
Reset Value
SYS_IRCTIEN
0xF4
R/W HIRC Trim Interrupt Enable Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
CLKEIEN
TFAILIEN
Reserved
Bits
Description
[31:3]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[2]
CLKEIEN
Clock Error Interrupt Enable Bit
This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim
operation.
If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an
interrupt will be triggered to notify the clock frequency is inaccuracy.
0 = Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU.
1 = Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU.
[1]
TFAILIEN
Trim Failure Interrupt Enable Bit
This bit controls if an interrupt will be triggered while HIRC trim value update limitation count
reached and HIRC frequency still not locked on target frequency set by
FREQSEL(SYS_IRCTCTL[1:0]).
If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an
interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
0 = Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU.
1 = Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU.
[0]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
