ISD94100 Series Technical Reference Manual
Sep 9, 2019
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1 = Transmit FIFO buffer is full.
[16]
TXEMPTY
Transmit FIFO Buffer Empty Indicator (Read Only)
0 = Transmit FIFO buffer is not empty.
1 = Transmit FIFO buffer is empty.
[15]
SPIENSTS
SPI Enable Status (Read Only)
0 = The SPI controller is disabled.
1 = The SPI controller is enabled.
Note:
The SPI peripheral clock is asynchronous with the system clock. In order to make
sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
[14:13]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[12]
RXTOIF
Receive Time-out Interrupt Flag
0 = No receive FIFO time-out event.
1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64
SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in
Slave mode. When the received FIFO buffer is read by software, the time-out status will be
cleared automatically.
Note:
This bit will be cleared by writing 1 to it.
[11]
RXOVIF
Receive FIFO Overrun Interrupt Flag
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be
set to 1.
0 = No FIFO is overrun.
1 = Receive FIFO is overrun.
Note:
This bit will be cleared by writing 1 to it.
[10]
RXTHIF
Receive FIFO Threshold Interrupt Flag (Read Only)
0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting
value of RXTH.
1 = The valid data count within the receive FIFO buffer is larger than the setting value of
RXTH.
[9]
RXFULL
Receive FIFO Buffer Full Indicator (Read Only)
0 = Receive FIFO buffer is not full.
1 = Receive FIFO buffer is full.
[8]
RXEMPTY
Receive FIFO Buffer Empty Indicator (Read Only)
0 = Receive FIFO buffer is not empty.
1 = Receive FIFO buffer is empty.
[7]
SLVURIF
Slave Mode TX Under Run Interrupt Flag
In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state,
this interrupt flag will be set to 1.
0 = No Slave TX under run event.
1 = Slave TX under run event occurs.
Note:
This bit will be cleared by writing 1 to it.
[6]
SLVBEIF
Slave Mode Bit Count Error Interrupt Flag
In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch
with DWIDTH, this interrupt flag will be set to 1.
0 = No Slave mode bit count error event.
1 = Slave mode bit count error event occurs.
Note:
If the slave select active but there is no any bus clock input, the SLVBEIF also active
when the slave select goes to inactive state. This bit will be cleared by writing 1 to it.
