ISD94100 Series Technical Reference Manual
Sep 9, 2019
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PDMA Interrupt Status Register (PDMA_INTSTS)
Register
Offset
R/W Description
Reset Value
PDMA_INTSTS
P 0x41C R/W PDMA Interrupt Status Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
REQTOF1
REQTOF0
7
6
5
4
3
2
1
0
Reserved
ALIGNF
TDIF
ABTIF
Bits
Description
[31:10]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[9]
REQTOF1
Request Time-out Flag for Channel 1
This flag indicates that PDMA controller has waited peripheral request for a period defined
by PDMA_TOC1, user can write 1 to clear these bits.
0 = No request time-out.
1 = Peripheral request time-out.
[8]
REQTOF0
Request Time-out Flag for Channel 0
This flag indicates that PDMA controller has waited peripheral request for a period defined
by PDMA_TOC0, user can write 1 to clear these bits.
0 = No request time-out.
1 = Peripheral request time-out.
[7:3]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[2]
ALIGNF
Transfer Alignment Interrupt Flag (Read Only)
0 = PDMA channel source address and destination address both follow transfer width
setting.
1 = PDMA channel source address or destination address is not follow transfer width
setting.
[1]
TDIF
Transfer Done Interrupt Flag (Read Only)
This bit indicates that PDMA controller has finished transmission; User can read
PDMA_TDSTS register to indicate which channel finished transfer.
0 = Not finished yet.
1 = PDMA channel has finished transmission.
[0]
ABTIF
PDMA Read/Write Target Abort Interrupt Flag (Read-only)
This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS
register to find which channel has target abort error.
0 = No AHB bus ERROR response received.
