ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Note:
If underflow event occurs in SPI Slave mode, there are two conditions which make SPI Slave
mode return to idle state and then goes for next transfer: (1) set TXRST to 1 (2) slave select signal
is changed to inactive state.
Slave TX under run interrupt
If the TX underflow event occurs, the SLVURIF (SPIn_STATUS[7]) will be set to 1 when slave
selection pin goes to inactive state. The SPI controller will issue a TX under run interrupt if the
SLVURIEN (SPIn_SSCTL[9]) is set to 1.
Note:
In SPI0 Slave 3-Wire mode, the slave selection signal is considered active all the time so
that user shall poll the TXUFIF (SPI0_STATUS[19]) to know if there is TX underflow event or not.
Receive Overrun interrupt
In Slave mode, if the receive FIFO buffer contains 4 (or 8 for SPI0) unread data, the RXFULL
(SPIn_STATUS[9]) will be set to 1 and the RXOVIF (SPIn_STATUS[11]) will be set to 1 if there is
more serial data is received from SPI bus and follow-up data will be dropped. The SPI controller
will issue an interrupt if the RXOVIEN (SPIn_FIFOCTL[5]) is set to 1.
Receive FIFO time-out interrupt
If there is a received data in the FIFO buffer and it is not read by software over 64 SPI peripheral
clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode, it will send
a RX time-out interrupt to the system if the RX time-out interrupt enable bit, RXTOIEN
(SPIn_FIFOCTL[4]), is set to 1.
Transmit FIFO interrupt
In FIFO mode, if the valid data count of the transmit FIFO buffer is less than or equal to the setting
value of TXTH (SPIn_FIFOCTL[30:28]), the transmit FIFO interrupt flag TXTHIF
(SPIn_STATUS[18]) will be set to 1. The SPI controller will generate a transmit FIFO interrupt to
the system if the transmit FIFO interrupt enable bit, TXTHIEN (SPIn_FIFOCTL[3]), is set to 1.
Receive FIFO interrupt
In FIFO mode, if the valid data count of the receive FIFO buffer is larger than the setting value of
RXTH (SPIn_FIFOCTL[26:24]), the receive FIFO interrupt flag RXTHIF (SPIn_STATUS[10]) will be
set to 1. The SPI controller will generate a receive FIFO interrupt to the system if the receive FIFO
interrupt enable bit, RXTHIEN (SPIn_FIFOCTL[2]), is set to 1.
6.14.5.13 I
2
S Mode
The SPI1~SPI2 controllers support I
2
S mode with PCM mode A, PCM mode B, MSB justified and
I
2
S data format. The bit count of an audio channel is determined by WDWIDTH (SPIn_I2SCTL[5:4]).
The transfer sequence is always first from the most significant bit, MSB. Data are read on rising
clock edge and are driven on falling clock edge.
In I
2
S data format, the MSB is sent and latched on the second clock of an audio channel. The
I2Sx_LRCLK signal indicates which audio channel is in transferring.
