ISD94100 Series Technical Reference Manual
Sep 9, 2019
Page
655
of 928
Rev1.09
IS
D
9
410
0
S
ER
IE
S
T
E
C
HN
ICA
L
RE
F
E
RE
NCE
M
AN
U
AL
I2C Status Register (I2C_STATUS)
Register
Offset
R/W Description
Reset Value
I2C_STATUS
0x0C
R
I
2
C Status Register 0
0x0000_00F8
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
STATUS
Bits
Description
[31:8]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[7:0]
STATUS
I
2
C Status
The three least significant bits are always 0. The five most significant bits contain the status
code. There are 28 possible status codes. When the content of I2C_STATUS is F8H, no
serial interrupt is requested. Others I2C_STATUS values correspond to defined I
2
C states.
When each of these states is entered, a status interrupt is requested (SI = 1). A valid status
code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one
cycle after SI has been reset by software. In addition, states 00H stands for a Bus Error. A
Bus Error occurs when a START or STOP condition is present at an illegal position in the
formation frame. Example of illegal position are during the serial transfer of an address byte,
a data byte or an acknowledge bit.
